{"id":"https://openalex.org/W2808593628","doi":"https://doi.org/10.1109/mce.2018.2816207","title":"Optimizing DSP Cores Using Design Transformation [Hardware Matters]","display_name":"Optimizing DSP Cores Using Design Transformation [Hardware Matters]","publication_year":2018,"publication_date":"2018-06-15","ids":{"openalex":"https://openalex.org/W2808593628","doi":"https://doi.org/10.1109/mce.2018.2816207","mag":"2808593628"},"language":"en","primary_location":{"id":"doi:10.1109/mce.2018.2816207","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mce.2018.2816207","pdf_url":null,"source":{"id":"https://openalex.org/S2483040032","display_name":"IEEE Consumer Electronics Magazine","issn_l":"2162-2248","issn":["2162-2248","2162-2256"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Consumer Electronics Magazine","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088900896","display_name":"Dipanjan Roy","orcid":null},"institutions":[{"id":"https://openalex.org/I64295750","display_name":"Indian Institute of Technology Indore","ror":"https://ror.org/01hhf7w52","country_code":"IN","type":"education","lineage":["https://openalex.org/I64295750"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Dipanjan Roy","raw_affiliation_strings":["Computer science and engineering, Indian Institute of Technology, Indore"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer science and engineering, Indian Institute of Technology, Indore","institution_ids":["https://openalex.org/I64295750"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5114672763","display_name":"Pallabi Sarkar","orcid":null},"institutions":[{"id":"https://openalex.org/I170979836","display_name":"Jadavpur University","ror":"https://ror.org/02af4h012","country_code":"IN","type":"education","lineage":["https://openalex.org/I170979836"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Pallabi Sarkar","raw_affiliation_strings":["Electronics and telecommunication engineering, Jadavpur University, Kolkata, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronics and telecommunication engineering, Jadavpur University, Kolkata, India","institution_ids":["https://openalex.org/I170979836"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007001727","display_name":"Anirban Sengupta","orcid":"https://orcid.org/0000-0002-8215-7903"},"institutions":[{"id":"https://openalex.org/I64295750","display_name":"Indian Institute of Technology Indore","ror":"https://ror.org/01hhf7w52","country_code":"IN","type":"education","lineage":["https://openalex.org/I64295750"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Anirban Sengupta","raw_affiliation_strings":["Computer science and engineering, Indian Institute of Technology, Indore"],"raw_orcid":"https://orcid.org/0000-0002-8215-7903","affiliations":[{"raw_affiliation_string":"Computer science and engineering, Indian Institute of Technology, Indore","institution_ids":["https://openalex.org/I64295750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5024123782","display_name":"Mrinal Kanti Naskar","orcid":"https://orcid.org/0000-0001-9357-887X"},"institutions":[{"id":"https://openalex.org/I170979836","display_name":"Jadavpur University","ror":"https://ror.org/02af4h012","country_code":"IN","type":"education","lineage":["https://openalex.org/I170979836"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Mrinal Kanti Naskar","raw_affiliation_strings":["Electronics and telecommunication engineering, Jadavpur University, Kolkata, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronics and telecommunication engineering, Jadavpur University, Kolkata, India","institution_ids":["https://openalex.org/I170979836"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5088900896"],"corresponding_institution_ids":["https://openalex.org/I64295750"],"apc_list":null,"apc_paid":null,"fwci":0.2627,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.50600046,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"7","issue":"4","first_page":"91","last_page":"94"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.8030860424041748},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7050790786743164},{"id":"https://openalex.org/keywords/distributive-property","display_name":"Distributive property","score":0.6291252970695496},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5782979130744934},{"id":"https://openalex.org/keywords/transformation","display_name":"Transformation (genetics)","score":0.542496919631958},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5049863457679749},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.48586505651474},{"id":"https://openalex.org/keywords/associative-property","display_name":"Associative property","score":0.46810340881347656},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2976788282394409},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08672234416007996}],"concepts":[{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.8030860424041748},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7050790786743164},{"id":"https://openalex.org/C11821877","wikidata":"https://www.wikidata.org/wiki/Q187959","display_name":"Distributive property","level":2,"score":0.6291252970695496},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5782979130744934},{"id":"https://openalex.org/C204241405","wikidata":"https://www.wikidata.org/wiki/Q461499","display_name":"Transformation (genetics)","level":3,"score":0.542496919631958},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5049863457679749},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.48586505651474},{"id":"https://openalex.org/C159423971","wikidata":"https://www.wikidata.org/wiki/Q177251","display_name":"Associative property","level":2,"score":0.46810340881347656},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2976788282394409},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08672234416007996},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C202444582","wikidata":"https://www.wikidata.org/wiki/Q837863","display_name":"Pure mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mce.2018.2816207","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mce.2018.2816207","pdf_url":null,"source":{"id":"https://openalex.org/S2483040032","display_name":"IEEE Consumer Electronics Magazine","issn_l":"2162-2248","issn":["2162-2248","2162-2256"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Consumer Electronics Magazine","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5099999904632568}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2067735763","https://openalex.org/W2469931790"],"related_works":["https://openalex.org/W2094667621","https://openalex.org/W2361934414","https://openalex.org/W3094589179","https://openalex.org/W3034071501","https://openalex.org/W4287760669","https://openalex.org/W2732052756","https://openalex.org/W4301372430","https://openalex.org/W2083279064","https://openalex.org/W4288102828","https://openalex.org/W4301372448"],"abstract_inverted_index":{"Reusable":[0],"digital":[1],"signal":[2],"processing":[3],"(DSP)":[4],"intellectual":[5],"property":[6],"(IF)":[7],"cores":[8,22,66],"play":[9],"a":[10,60,123],"crucial":[11,24],"role":[12],"in":[13],"numerous":[14],"domains,":[15],"including":[16],"consumer":[17],"electronics.":[18],"However,":[19],"optimizing":[20,64],"DSP":[21,65,81],"is":[23,75],"for":[25,63],"the":[26,80,85,88,107],"reduction":[27],"of":[28,87,116,121],"design":[29,50,68,98],"area,":[30],"delay,":[31],"power,":[32],"and":[33,52,78,112],"so":[34],"forth":[35],"[1],":[36,55],"[2].":[37,56],"Though":[38],"several":[39],"optimization":[40],"techniques":[41],"using":[42,67],"evolutionary":[43],"algorithms":[44],"have":[45],"been":[46],"proposed,":[47],"they":[48],"incur":[49],"overhead":[51],"exploration":[53],"time":[54],"This":[57],"column":[58],"proposes":[59],"novel":[61],"methodology":[62],"transformation":[69],"during":[70],"architectural":[71],"synthesis.":[72],"The":[73,92],"goal":[74],"to":[76],"transform":[77],"optimize":[79],"application":[82,89],"such":[83],"that":[84],"functionality":[86],"remains":[90],"unperturbed.":[91],"proposed":[93],"approach":[94],"optimizes":[95],"an":[96],"IP":[97,129],"through":[99],"multiple":[100],"transformations":[101,118],"based":[102],"on":[103],"algebraic":[104],"laws,":[105],"i.e.,":[106],"associative":[108],"law,":[109,111],"commutative":[110],"distributive":[113],"law.":[114],"All":[115],"these":[117],"are":[119],"capable":[120],"generating":[122],"functionally":[124],"equivalent":[125],"but":[126],"structurally":[127],"transformed":[128],"design.":[130]},"counts_by_year":[{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
