{"id":"https://openalex.org/W1977966390","doi":"https://doi.org/10.1109/mc.2004.1260732","title":"Programming models for hybrid CPU/FPGA chips","display_name":"Programming models for hybrid CPU/FPGA chips","publication_year":2004,"publication_date":"2004-01-01","ids":{"openalex":"https://openalex.org/W1977966390","doi":"https://doi.org/10.1109/mc.2004.1260732","mag":"1977966390"},"language":"en","primary_location":{"id":"doi:10.1109/mc.2004.1260732","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mc.2004.1260732","pdf_url":null,"source":{"id":"https://openalex.org/S178916657","display_name":"Computer","issn_l":"0018-9162","issn":["0018-9162","1558-0814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320439","host_organization_name":"IEEE Computer Society","host_organization_lineage":["https://openalex.org/P4310320439","https://openalex.org/P4310319808"],"host_organization_lineage_names":["IEEE Computer Society","Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Computer","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5062434121","display_name":"David Andrews","orcid":"https://orcid.org/0000-0003-1464-7107"},"institutions":[{"id":"https://openalex.org/I146416000","display_name":"University of Kansas","ror":"https://ror.org/001tmjg57","country_code":"US","type":"education","lineage":["https://openalex.org/I146416000"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D. Andrews","raw_affiliation_strings":["University of Kansas, USA","Kansas University, Lawrence, KS, USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Kansas, USA","institution_ids":["https://openalex.org/I146416000"]},{"raw_affiliation_string":"Kansas University, Lawrence, KS, USA#TAB#","institution_ids":["https://openalex.org/I146416000"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111946679","display_name":"D. Niehaus","orcid":null},"institutions":[{"id":"https://openalex.org/I146416000","display_name":"University of Kansas","ror":"https://ror.org/001tmjg57","country_code":"US","type":"education","lineage":["https://openalex.org/I146416000"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D. Niehaus","raw_affiliation_strings":["University of Kansas, USA","Kansas University, Lawrence, KS, USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Kansas, USA","institution_ids":["https://openalex.org/I146416000"]},{"raw_affiliation_string":"Kansas University, Lawrence, KS, USA#TAB#","institution_ids":["https://openalex.org/I146416000"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065468199","display_name":"Peter J. Ashenden","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"P. Ashenden","raw_affiliation_strings":["Ashenden Designs, Australia","[Ashenden Designs, Australia]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Ashenden Designs, Australia","institution_ids":[]},{"raw_affiliation_string":"[Ashenden Designs, Australia]","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":5.3002,"has_fulltext":false,"cited_by_count":55,"citation_normalized_percentile":{"value":0.95591109,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"37","issue":"1","first_page":"118","last_page":"120"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9883000254631042,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7781273126602173},{"id":"https://openalex.org/keywords/time-to-market","display_name":"Time to market","score":0.7672538161277771},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6833111047744751},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.631765604019165},{"id":"https://openalex.org/keywords/personalization","display_name":"Personalization","score":0.5129703879356384},{"id":"https://openalex.org/keywords/programming-paradigm","display_name":"Programming paradigm","score":0.5055818557739258},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.370938777923584},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2584592401981354}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7781273126602173},{"id":"https://openalex.org/C2779229675","wikidata":"https://www.wikidata.org/wiki/Q445235","display_name":"Time to market","level":2,"score":0.7672538161277771},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6833111047744751},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.631765604019165},{"id":"https://openalex.org/C183003079","wikidata":"https://www.wikidata.org/wiki/Q1000371","display_name":"Personalization","level":2,"score":0.5129703879356384},{"id":"https://openalex.org/C34165917","wikidata":"https://www.wikidata.org/wiki/Q188267","display_name":"Programming paradigm","level":2,"score":0.5055818557739258},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.370938777923584},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2584592401981354},{"id":"https://openalex.org/C136764020","wikidata":"https://www.wikidata.org/wiki/Q466","display_name":"World Wide Web","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mc.2004.1260732","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mc.2004.1260732","pdf_url":null,"source":{"id":"https://openalex.org/S178916657","display_name":"Computer","issn_l":"0018-9162","issn":["0018-9162","1558-0814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320439","host_organization_name":"IEEE Computer Society","host_organization_lineage":["https://openalex.org/P4310320439","https://openalex.org/P4310319808"],"host_organization_lineage_names":["IEEE Computer Society","Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Computer","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2109940557","https://openalex.org/W2466832359","https://openalex.org/W2111241003","https://openalex.org/W1582019636","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2109907925","https://openalex.org/W4247963789","https://openalex.org/W2051573100"],"abstract_inverted_index":{"Designers":[0],"of":[1,25,47,62,143],"embedded":[2],"and":[3,32,64,91,117,128,156],"real-time":[4],"systems":[5],"are":[6,41,68,134],"continually":[7],"challenged":[8],"to":[9,28,34,81,93,98,120],"meet":[10,99],"tighter":[11],"system":[12],"requirements":[13],"at":[14,113],"better":[15],"price-performance":[16],"ratios.":[17],"Best-practice":[18],"methods":[19],"have":[20],"long":[21],"promoted":[22],"the":[23,53,58,73,100,166],"use":[24],"commercial-off-the-shelf":[26],"components":[27,39,88,106,133],"reduce":[29],"design":[30,60],"costs":[31,90,116],"time":[33,92],"market,":[35],"but":[36,95,112],"creating":[37],"COTS":[38,87,141],"that":[40,152,164],"reusable":[42],"in":[43,56,79],"a":[44,154,161],"wide":[45],"range":[46],"applications":[48],"remains":[49],"difficult.":[50],"In":[51],"part,":[52],"challenge":[54],"lies":[55],"satisfying":[57],"contradictory":[59],"forces":[61,77],"generalization":[63],"specialization.":[65],"Systems":[66],"designers":[67],"all":[69],"too":[70],"familiar":[71],"with":[72],"tension":[74],"these":[75],"opposing":[76],"cause":[78],"trying":[80],"balance":[82],"cost":[83],"versus":[84],"performance.":[85],"Adopting":[86],"reduces":[89],"market":[94],"often":[96],"fails":[97],"most":[101],"demanding":[102],"performance":[103,111],"requirements;":[104],"custom-designed":[105],"can":[107],"achieve":[108],"significantly":[109],"higher":[110],"greater":[114],"development":[115],"longer":[118],"times":[119],"market.":[121],"Emerging":[122],"hybrid":[123],"chips":[124],"containing":[125],"both":[126],"CPU":[127,155],"field-programmable":[129],"gate":[130],"array":[131],"(FPGA)":[132],"an":[135],"exciting":[136],"new":[137],"development.":[138],"They":[139],"promise":[140],"economies":[142],"scale":[144],"while":[145],"also":[146],"supporting":[147],"significant":[148],"hardware":[149],"customization.":[150],"Components":[151],"combine":[153],"reconfigurable":[157],"logic":[158],"gates":[159],"need":[160],"programming":[162],"model":[163],"abstracts":[165],"computational":[167],"hardware.":[168]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":3},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}