{"id":"https://openalex.org/W2076000316","doi":"https://doi.org/10.1109/mc.1974.6323496","title":"Concurrent simulation of nearly identical digital networks","display_name":"Concurrent simulation of nearly identical digital networks","publication_year":1974,"publication_date":"1974-04-01","ids":{"openalex":"https://openalex.org/W2076000316","doi":"https://doi.org/10.1109/mc.1974.6323496","mag":"2076000316"},"language":"en","primary_location":{"id":"doi:10.1109/mc.1974.6323496","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mc.1974.6323496","pdf_url":null,"source":{"id":"https://openalex.org/S178916657","display_name":"Computer","issn_l":"0018-9162","issn":["0018-9162","1558-0814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320439","host_organization_name":"IEEE Computer Society","host_organization_lineage":["https://openalex.org/P4310320439","https://openalex.org/P4310319808"],"host_organization_lineage_names":["IEEE Computer Society","Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Computer","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111623973","display_name":"E. Ulrich","orcid":null},"institutions":[{"id":"https://openalex.org/I4210152463","display_name":"TE Laboratories (Ireland)","ror":"https://ror.org/05th81a29","country_code":"IE","type":"company","lineage":["https://openalex.org/I4210152463"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"E. G. Ulrich","raw_affiliation_strings":["GTE Laboratories, Inc., USA","GTE Laboratories Inc"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"GTE Laboratories, Inc., USA","institution_ids":[]},{"raw_affiliation_string":"GTE Laboratories Inc","institution_ids":["https://openalex.org/I4210152463"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108969733","display_name":"T. Baker","orcid":"https://orcid.org/0000-0002-7623-3105"},"institutions":[{"id":"https://openalex.org/I4210152463","display_name":"TE Laboratories (Ireland)","ror":"https://ror.org/05th81a29","country_code":"IE","type":"company","lineage":["https://openalex.org/I4210152463"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"T. Baker","raw_affiliation_strings":["GTE Laboratories, Inc., USA","GTE Laboratories Inc"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"GTE Laboratories, Inc., USA","institution_ids":[]},{"raw_affiliation_string":"GTE Laboratories Inc","institution_ids":["https://openalex.org/I4210152463"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210152463"],"apc_list":null,"apc_paid":null,"fwci":1.2257,"has_fulltext":false,"cited_by_count":236,"citation_normalized_percentile":{"value":0.77993528,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"7","issue":"4","first_page":"39","last_page":"44"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8317996263504028},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.5141282677650452},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.5094049572944641},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.49499577283859253},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.4356895387172699},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.43328842520713806},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.2657909393310547},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08310428261756897}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8317996263504028},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.5141282677650452},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.5094049572944641},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.49499577283859253},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.4356895387172699},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.43328842520713806},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.2657909393310547},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08310428261756897},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C165205528","wikidata":"https://www.wikidata.org/wiki/Q83371","display_name":"Seismology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mc.1974.6323496","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mc.1974.6323496","pdf_url":null,"source":{"id":"https://openalex.org/S178916657","display_name":"Computer","issn_l":"0018-9162","issn":["0018-9162","1558-0814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320439","host_organization_name":"IEEE Computer Society","host_organization_lineage":["https://openalex.org/P4310320439","https://openalex.org/P4310319808"],"host_organization_lineage_names":["IEEE Computer Society","Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Computer","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2091833418","https://openalex.org/W2021253405","https://openalex.org/W2913077774","https://openalex.org/W2145089576","https://openalex.org/W1986228509","https://openalex.org/W2147400189","https://openalex.org/W2340957901","https://openalex.org/W1991935474","https://openalex.org/W2786111245","https://openalex.org/W2117873690"],"abstract_inverted_index":{"Test":[0],"patterns":[1],"for":[2,40],"testing":[3],"digital":[4],"circuits":[5],"are":[6],"usually":[7],"checked":[8],"on":[9],"a":[10,29],"test":[11,30],"verification":[12,31],"program":[13,32],"to":[14],"determine":[15],"if":[16],"all":[17],"or":[18],"most":[19],"of":[20],"the":[21],"possible":[22,42],"faults":[23],"will":[24],"be":[25,34],"detected.":[26],"Historically,":[27],"such":[28],"would":[33],"accomplished":[35],"with":[36],"many":[37],"simulations:":[38],"one":[39],"each":[41],"fault.":[43]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2014,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
