{"id":"https://openalex.org/W2148974576","doi":"https://doi.org/10.1109/mascot.2002.1167064","title":"Cone clustering principles for parallel logic simulation","display_name":"Cone clustering principles for parallel logic simulation","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W2148974576","doi":"https://doi.org/10.1109/mascot.2002.1167064","mag":"2148974576"},"language":"en","primary_location":{"id":"doi:10.1109/mascot.2002.1167064","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mascot.2002.1167064","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 10th IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunications Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5013876035","display_name":"K. Hering","orcid":null},"institutions":[{"id":"https://openalex.org/I2610724","display_name":"Chemnitz University of Technology","ror":"https://ror.org/00a208s56","country_code":"DE","type":"education","lineage":["https://openalex.org/I2610724"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"K. Hering","raw_affiliation_strings":["Chemnitz University of Technology, Chemnitz, Germany"],"affiliations":[{"raw_affiliation_string":"Chemnitz University of Technology, Chemnitz, Germany","institution_ids":["https://openalex.org/I2610724"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025388659","display_name":"Robert Reilein","orcid":null},"institutions":[{"id":"https://openalex.org/I2610724","display_name":"Chemnitz University of Technology","ror":"https://ror.org/00a208s56","country_code":"DE","type":"education","lineage":["https://openalex.org/I2610724"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"R. Reilein","raw_affiliation_strings":["Chemnitz University of Technology, Chemnitz, Germany"],"affiliations":[{"raw_affiliation_string":"Chemnitz University of Technology, Chemnitz, Germany","institution_ids":["https://openalex.org/I2610724"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5023281382","display_name":"S. Trautmann","orcid":null},"institutions":[{"id":"https://openalex.org/I2610724","display_name":"Chemnitz University of Technology","ror":"https://ror.org/00a208s56","country_code":"DE","type":"education","lineage":["https://openalex.org/I2610724"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"S. Trautmann","raw_affiliation_strings":["Chemnitz University of Technology, Chemnitz, Germany"],"affiliations":[{"raw_affiliation_string":"Chemnitz University of Technology, Chemnitz, Germany","institution_ids":["https://openalex.org/I2610724"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5013876035"],"corresponding_institution_ids":["https://openalex.org/I2610724"],"apc_list":null,"apc_paid":null,"fwci":0.3477,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.65531247,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"93","last_page":"100"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cluster-analysis","display_name":"Cluster analysis","score":0.7664204835891724},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7264269590377808},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6549171209335327},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.6052874326705933},{"id":"https://openalex.org/keywords/logic-simulation","display_name":"Logic simulation","score":0.5750178098678589},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.5262131690979004},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.48429861664772034},{"id":"https://openalex.org/keywords/ibm","display_name":"IBM","score":0.480229914188385},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.46171140670776367},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.45985323190689087},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4525349736213684},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4166828393936157},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3926779329776764},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.351278692483902},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3380414843559265},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.21681222319602966},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.1587877869606018}],"concepts":[{"id":"https://openalex.org/C73555534","wikidata":"https://www.wikidata.org/wiki/Q622825","display_name":"Cluster analysis","level":2,"score":0.7664204835891724},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7264269590377808},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6549171209335327},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.6052874326705933},{"id":"https://openalex.org/C64859876","wikidata":"https://www.wikidata.org/wiki/Q173673","display_name":"Logic simulation","level":3,"score":0.5750178098678589},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.5262131690979004},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.48429861664772034},{"id":"https://openalex.org/C70388272","wikidata":"https://www.wikidata.org/wiki/Q5968558","display_name":"IBM","level":2,"score":0.480229914188385},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.46171140670776367},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.45985323190689087},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4525349736213684},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4166828393936157},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3926779329776764},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.351278692483902},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3380414843559265},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.21681222319602966},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.1587877869606018},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.0},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mascot.2002.1167064","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mascot.2002.1167064","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 10th IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunications Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.47999998927116394,"display_name":"Decent work and economic growth","id":"https://metadata.un.org/sdg/8"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1984283136","https://openalex.org/W2045271686","https://openalex.org/W2102061396","https://openalex.org/W2102695924","https://openalex.org/W2115214915","https://openalex.org/W2139724346","https://openalex.org/W2155882878","https://openalex.org/W2171587453","https://openalex.org/W2610550445","https://openalex.org/W4242963173","https://openalex.org/W6656844882","https://openalex.org/W6986268882"],"related_works":["https://openalex.org/W2386022279","https://openalex.org/W2101877870","https://openalex.org/W2370649629","https://openalex.org/W3129977055","https://openalex.org/W2356140560","https://openalex.org/W1511082991","https://openalex.org/W2362510906","https://openalex.org/W4321609265","https://openalex.org/W2243536805","https://openalex.org/W2113499682"],"abstract_inverted_index":{"Parallelization":[0],"following":[1],"the":[2,59],"replicated":[3],"worker":[4],"principle":[5],"can":[6,48],"significantly":[7],"accelerate":[8],"functional":[9],"logic":[10,56,93],"simulation":[11],"of":[12,17,54,68,79,91,121],"microprocessor":[13],"structures.":[14],"Successful":[15],"application":[16],"this":[18],"method":[19],"strongly":[20],"depends":[21],"on":[22,87],"circuit":[23,70],"model":[24,71,90],"partitioning.":[25],"We":[26,74],"have":[27,58],"developed":[28],"a":[29,69,88,119],"hierarchical":[30],"partitioning":[31,37],"strategy":[32],"with":[33,99],"prepartitioning":[34],"and":[35,76,123],"main":[36],"as":[38,43,51],"core":[39],"phases":[40],"that":[41],"appear":[42],"bottom-up":[44],"cone":[45,81],"clustering.":[46],"Cones":[47],"be":[49],"seen":[50],"special":[52],"areas":[53],"combinational":[55],"which":[57,84],"ability":[60],"to":[61,101,113],"directly":[62],"influence":[63],"storing":[64],"or":[65],"output":[66],"elements":[67,117],"under":[72],"consideration.":[73],"describe":[75],"compare":[77],"three":[78],"our":[80],"clustering":[82],"techniques":[83],"are":[85,97],"based":[86],"formal":[89],"parallel":[92],"simulation.":[94],"Experimental":[95],"results":[96],"given":[98],"respect":[100],"IBM":[102],"processor":[103],"structures":[104],"ranging":[105],"in":[106],"their":[107],"size":[108],"from":[109],"several":[110,114],"hundred":[111],"thousand":[112],"million":[115],"basic":[116],"at":[118],"mixture":[120],"register-transfer-":[122],"gate":[124],"level.":[125]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}