{"id":"https://openalex.org/W4415820821","doi":"https://doi.org/10.1109/lssc.2025.3628176","title":"A 37.8 Mb/mm\u00b2 SRAM in Intel 18A Technology Featuring a Resistive Supply-Line Write Scheme and Write-Assist With Parallel Boost Injection","display_name":"A 37.8 Mb/mm\u00b2 SRAM in Intel 18A Technology Featuring a Resistive Supply-Line Write Scheme and Write-Assist With Parallel Boost Injection","publication_year":2025,"publication_date":"2025-01-01","ids":{"openalex":"https://openalex.org/W4415820821","doi":"https://doi.org/10.1109/lssc.2025.3628176"},"language":null,"primary_location":{"id":"doi:10.1109/lssc.2025.3628176","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lssc.2025.3628176","pdf_url":null,"source":{"id":"https://openalex.org/S4210192596","display_name":"IEEE Solid-State Circuits Letters","issn_l":"2573-9603","issn":["2573-9603"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Solid-State Circuits Letters","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5071792287","display_name":"Harold Pilo","orcid":"https://orcid.org/0009-0002-6782-965X"},"institutions":[{"id":"https://openalex.org/I4210087851","display_name":"Sunnyvale Public Library","ror":"https://ror.org/006afd344","country_code":"US","type":"archive","lineage":["https://openalex.org/I4210087851"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Harold Pilo","raw_affiliation_strings":["Sunnyvale Inc., Sunnyvale, CA, USA"],"raw_orcid":"https://orcid.org/0009-0002-6782-965X","affiliations":[{"raw_affiliation_string":"Sunnyvale Inc., Sunnyvale, CA, USA","institution_ids":["https://openalex.org/I4210087851"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073674118","display_name":"Manish Arora","orcid":"https://orcid.org/0000-0002-3350-4657"},"institutions":[{"id":"https://openalex.org/I4210087851","display_name":"Sunnyvale Public Library","ror":"https://ror.org/006afd344","country_code":"US","type":"archive","lineage":["https://openalex.org/I4210087851"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Manish Arora","raw_affiliation_strings":["Sunnyvale Inc., Sunnyvale, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sunnyvale Inc., Sunnyvale, CA, USA","institution_ids":["https://openalex.org/I4210087851"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111861029","display_name":"Chien-An Lai","orcid":"https://orcid.org/0009-0005-4384-4777"},"institutions":[{"id":"https://openalex.org/I4210087851","display_name":"Sunnyvale Public Library","ror":"https://ror.org/006afd344","country_code":"US","type":"archive","lineage":["https://openalex.org/I4210087851"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chien-An Lai","raw_affiliation_strings":["Sunnyvale Inc., Sunnyvale, CA, USA"],"raw_orcid":"https://orcid.org/0009-0005-4384-4777","affiliations":[{"raw_affiliation_string":"Sunnyvale Inc., Sunnyvale, CA, USA","institution_ids":["https://openalex.org/I4210087851"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Mike Lee","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087851","display_name":"Sunnyvale Public Library","ror":"https://ror.org/006afd344","country_code":"US","type":"archive","lineage":["https://openalex.org/I4210087851"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mike Lee","raw_affiliation_strings":["Sunnyvale Inc., Sunnyvale, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sunnyvale Inc., Sunnyvale, CA, USA","institution_ids":["https://openalex.org/I4210087851"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5119213297","display_name":"Zack Lo","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087851","display_name":"Sunnyvale Public Library","ror":"https://ror.org/006afd344","country_code":"US","type":"archive","lineage":["https://openalex.org/I4210087851"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zack Lo","raw_affiliation_strings":["Sunnyvale Inc., Sunnyvale, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sunnyvale Inc., Sunnyvale, CA, USA","institution_ids":["https://openalex.org/I4210087851"]}]},{"author_position":"last","author":{"id":null,"display_name":"Mayur Randeria","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087851","display_name":"Sunnyvale Public Library","ror":"https://ror.org/006afd344","country_code":"US","type":"archive","lineage":["https://openalex.org/I4210087851"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mayur Randeria","raw_affiliation_strings":["Sunnyvale Inc., Sunnyvale, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sunnyvale Inc., Sunnyvale, CA, USA","institution_ids":["https://openalex.org/I4210087851"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210087851"],"apc_list":null,"apc_paid":null,"fwci":0.3267,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.58141064,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":97},"biblio":{"volume":"8","issue":null,"first_page":"357","last_page":"360"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.8705999851226807,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.8705999851226807,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.017999999225139618,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.01730000041425228,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7702000141143799},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.46320000290870667},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.45739999413490295},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.43459999561309814},{"id":"https://openalex.org/keywords/access-time","display_name":"Access time","score":0.4097000062465668},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4000000059604645},{"id":"https://openalex.org/keywords/resistive-touchscreen","display_name":"Resistive touchscreen","score":0.3862999975681305},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.3490000069141388},{"id":"https://openalex.org/keywords/standby-power","display_name":"Standby power","score":0.3425999879837036}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7702000141143799},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5543000102043152},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5011000037193298},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.46320000290870667},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.45739999413490295},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.44449999928474426},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4375},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.43459999561309814},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.41519999504089355},{"id":"https://openalex.org/C194080101","wikidata":"https://www.wikidata.org/wiki/Q46306","display_name":"Access time","level":2,"score":0.4097000062465668},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4000000059604645},{"id":"https://openalex.org/C6899612","wikidata":"https://www.wikidata.org/wiki/Q852911","display_name":"Resistive touchscreen","level":2,"score":0.3862999975681305},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.3490000069141388},{"id":"https://openalex.org/C7140552","wikidata":"https://www.wikidata.org/wiki/Q1366402","display_name":"Standby power","level":3,"score":0.3425999879837036},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.3402999937534332},{"id":"https://openalex.org/C2776321774","wikidata":"https://www.wikidata.org/wiki/Q891131","display_name":"Read-write memory","level":3,"score":0.3375999927520752},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.31619998812675476},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.3111000061035156},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.3109000027179718},{"id":"https://openalex.org/C74064498","wikidata":"https://www.wikidata.org/wiki/Q3396184","display_name":"Radio frequency","level":2,"score":0.303600013256073},{"id":"https://openalex.org/C43363307","wikidata":"https://www.wikidata.org/wiki/Q1651623","display_name":"Racetrack memory","level":5,"score":0.30149999260902405},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.29919999837875366},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.2971000075340271},{"id":"https://openalex.org/C21881925","wikidata":"https://www.wikidata.org/wiki/Q3503313","display_name":"Power density","level":3,"score":0.296099990606308},{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.2921999990940094},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.27300000190734863},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.2572999894618988},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2535000145435333}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/lssc.2025.3628176","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lssc.2025.3628176","pdf_url":null,"source":{"id":"https://openalex.org/S4210192596","display_name":"IEEE Solid-State Circuits Letters","issn_l":"2573-9603","issn":["2573-9603"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Solid-State Circuits Letters","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W3015213341","https://openalex.org/W3048906546","https://openalex.org/W4286571776","https://openalex.org/W4385213884","https://openalex.org/W4385223676","https://openalex.org/W4392746569","https://openalex.org/W4408182241","https://openalex.org/W4408183030","https://openalex.org/W4408183204","https://openalex.org/W4412964263"],"related_works":[],"abstract_inverted_index":{"A":[0],"high-density,":[1],"SRAM-based":[2],"Register":[3],"File":[4],"(RF)":[5],"has":[6],"been":[7],"demonstrated":[8],"in":[9,52],"Intel":[10],"18A":[11],"Technology":[12],"1,":[13,58],"2":[14],"featuring":[15],"RibbonFET":[16],"GAA":[17],"transistors":[18],"and":[19,34,37,72],"a":[20,39,65],"Back":[21],"Side":[22],"Power":[23],"Delivery":[24],"Network":[25],"(BSDPN).":[26],"The":[27],"RF":[28,51],"is":[29,62],"optimized":[30],"for":[31,49,81],"high":[32],"density":[33,40,45],"array":[35],"efficiency":[36],"achieves":[38],"of":[41,88],"37.8Mb/mm2,":[42],"the":[43,53,78],"highest":[44],"reported":[46],"to":[47],"date":[48],"an":[50],"most":[54,82],"advanced":[55],"technology":[56],"nodes":[57],"3,":[59],"4.":[60],"It":[61],"implemented":[63],"with":[64,85],"conventional":[66],"Bitline":[67],"(BL),":[68],"two-bank":[69],"memory":[70],"architecture":[71],"it":[73],"can":[74],"be":[75],"used":[76],"as":[77],"SRAM":[79],"workhorse":[80],"SoC":[83],"applications":[84],"maximum":[86],"bit-count":[87],"262Kb.":[89]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2026-07-15T18:14:33.161393","created_date":"2025-11-03T00:00:00"}