{"id":"https://openalex.org/W4313150973","doi":"https://doi.org/10.1109/les.2022.3218289","title":"Accelerating the Verification of Forward Error Correction Decoders by PCIe FPGA Cards","display_name":"Accelerating the Verification of Forward Error Correction Decoders by PCIe FPGA Cards","publication_year":2022,"publication_date":"2022-11-04","ids":{"openalex":"https://openalex.org/W4313150973","doi":"https://doi.org/10.1109/les.2022.3218289"},"language":"en","primary_location":{"id":"doi:10.1109/les.2022.3218289","is_oa":false,"landing_page_url":"https://doi.org/10.1109/les.2022.3218289","pdf_url":null,"source":{"id":"https://openalex.org/S22443479","display_name":"IEEE Embedded Systems Letters","issn_l":"1943-0663","issn":["1943-0663","1943-0671"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Embedded Systems Letters","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://repositorio.unican.es/xmlui/bitstream/10902/29938/2/AcceleratingVerificationForward.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002443302","display_name":"Daniel Su\u00e1rez","orcid":"https://orcid.org/0000-0002-5722-4051"},"institutions":[{"id":"https://openalex.org/I13134134","display_name":"Universidad de Cantabria","ror":"https://ror.org/046ffzj20","country_code":"ES","type":"education","lineage":["https://openalex.org/I13134134"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"Daniel Su\u00e1rez","raw_affiliation_strings":["Microelectronics Engineering Group, Universidad de Cantabria, Santander, Spain"],"affiliations":[{"raw_affiliation_string":"Microelectronics Engineering Group, Universidad de Cantabria, Santander, Spain","institution_ids":["https://openalex.org/I13134134"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025138641","display_name":"V\u00edctor Fern\u00e1ndez","orcid":"https://orcid.org/0000-0003-0614-151X"},"institutions":[{"id":"https://openalex.org/I13134134","display_name":"Universidad de Cantabria","ror":"https://ror.org/046ffzj20","country_code":"ES","type":"education","lineage":["https://openalex.org/I13134134"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"V\u00edctor Fern\u00e1ndez","raw_affiliation_strings":["Microelectronics Engineering Group, Universidad de Cantabria, Santander, Spain"],"affiliations":[{"raw_affiliation_string":"Microelectronics Engineering Group, Universidad de Cantabria, Santander, Spain","institution_ids":["https://openalex.org/I13134134"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077809133","display_name":"H\u00e9ctor Posadas","orcid":"https://orcid.org/0000-0002-1427-7524"},"institutions":[{"id":"https://openalex.org/I13134134","display_name":"Universidad de Cantabria","ror":"https://ror.org/046ffzj20","country_code":"ES","type":"education","lineage":["https://openalex.org/I13134134"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"H\u00e9ctor Posadas","raw_affiliation_strings":["Microelectronics Engineering Group, Universidad de Cantabria, Santander, Spain"],"affiliations":[{"raw_affiliation_string":"Microelectronics Engineering Group, Universidad de Cantabria, Santander, Spain","institution_ids":["https://openalex.org/I13134134"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101992779","display_name":"Pablo S\u00e1nchez","orcid":"https://orcid.org/0000-0001-7363-5814"},"institutions":[{"id":"https://openalex.org/I13134134","display_name":"Universidad de Cantabria","ror":"https://ror.org/046ffzj20","country_code":"ES","type":"education","lineage":["https://openalex.org/I13134134"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Pablo S\u00e1nchez","raw_affiliation_strings":["Microelectronics Engineering Group, Universidad de Cantabria, Santander, Spain"],"affiliations":[{"raw_affiliation_string":"Microelectronics Engineering Group, Universidad de Cantabria, Santander, Spain","institution_ids":["https://openalex.org/I13134134"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5002443302"],"corresponding_institution_ids":["https://openalex.org/I13134134"],"apc_list":null,"apc_paid":null,"fwci":0.2839,"has_fulltext":true,"cited_by_count":3,"citation_normalized_percentile":{"value":0.59584553,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"15","issue":"3","first_page":"157","last_page":"160"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11321","display_name":"Error Correcting Code Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11321","display_name":"Error Correcting Code Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8957975506782532},{"id":"https://openalex.org/keywords/pci-express","display_name":"PCI Express","score":0.8814423680305481},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6819676160812378},{"id":"https://openalex.org/keywords/testbed","display_name":"Testbed","score":0.6262214779853821},{"id":"https://openalex.org/keywords/toolchain","display_name":"Toolchain","score":0.5532257556915283},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.548609733581543},{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.4938660264015198},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.4583771228790283},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4141475558280945},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.35396015644073486},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3362997770309448},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.26920363306999207},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.21009621024131775},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.10915178060531616}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8957975506782532},{"id":"https://openalex.org/C64270927","wikidata":"https://www.wikidata.org/wiki/Q206924","display_name":"PCI Express","level":3,"score":0.8814423680305481},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6819676160812378},{"id":"https://openalex.org/C31395832","wikidata":"https://www.wikidata.org/wiki/Q1318674","display_name":"Testbed","level":2,"score":0.6262214779853821},{"id":"https://openalex.org/C2777062904","wikidata":"https://www.wikidata.org/wiki/Q545406","display_name":"Toolchain","level":3,"score":0.5532257556915283},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.548609733581543},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.4938660264015198},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.4583771228790283},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4141475558280945},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.35396015644073486},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3362997770309448},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.26920363306999207},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.21009621024131775},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.10915178060531616},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/les.2022.3218289","is_oa":false,"landing_page_url":"https://doi.org/10.1109/les.2022.3218289","pdf_url":null,"source":{"id":"https://openalex.org/S22443479","display_name":"IEEE Embedded Systems Letters","issn_l":"1943-0663","issn":["1943-0663","1943-0671"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Embedded Systems Letters","raw_type":"journal-article"},{"id":"pmh:oai:repositorio.unican.es:10902/29938","is_oa":true,"landing_page_url":"https://hdl.handle.net/10902/29938","pdf_url":"https://repositorio.unican.es/xmlui/bitstream/10902/29938/2/AcceleratingVerificationForward.pdf","source":{"id":"https://openalex.org/S4306400398","display_name":"UCrea (University of Cantabria)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I13134134","host_organization_name":"Universidad de Cantabria","host_organization_lineage":["https://openalex.org/I13134134"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Embedded Systems Letters, 2023, 15(3), 157-160","raw_type":"acceptedVersion"}],"best_oa_location":{"id":"pmh:oai:repositorio.unican.es:10902/29938","is_oa":true,"landing_page_url":"https://hdl.handle.net/10902/29938","pdf_url":"https://repositorio.unican.es/xmlui/bitstream/10902/29938/2/AcceleratingVerificationForward.pdf","source":{"id":"https://openalex.org/S4306400398","display_name":"UCrea (University of Cantabria)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I13134134","host_organization_name":"Universidad de Cantabria","host_organization_lineage":["https://openalex.org/I13134134"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Embedded Systems Letters, 2023, 15(3), 157-160","raw_type":"acceptedVersion"},"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.4399999976158142,"id":"https://metadata.un.org/sdg/9"}],"awards":[{"id":"https://openalex.org/G6220928131","display_name":null,"funder_award_id":"DAIS","funder_id":"https://openalex.org/F4320327207","funder_display_name":"Electronic Components and Systems for European Leadership"},{"id":"https://openalex.org/G7146744822","display_name":null,"funder_award_id":"pci2021-121988","funder_id":"https://openalex.org/F4320322930","funder_display_name":"Ministerio de Ciencia e Innovaci\u00f3n"},{"id":"https://openalex.org/G7452744387","display_name":null,"funder_award_id":"PID2020-116417RB-C43","funder_id":"https://openalex.org/F4320322930","funder_display_name":"Ministerio de Ciencia e Innovaci\u00f3n"}],"funders":[{"id":"https://openalex.org/F4320322930","display_name":"Ministerio de Ciencia e Innovaci\u00f3n","ror":"https://ror.org/034900433"},{"id":"https://openalex.org/F4320327207","display_name":"Electronic Components and Systems for European Leadership","ror":null}],"has_content":{"grobid_xml":false,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W4313150973.pdf"},"referenced_works_count":15,"referenced_works":["https://openalex.org/W1966085625","https://openalex.org/W1970010894","https://openalex.org/W2095595785","https://openalex.org/W2103990891","https://openalex.org/W2117106078","https://openalex.org/W2117954347","https://openalex.org/W2175102988","https://openalex.org/W3005538120","https://openalex.org/W3089212530","https://openalex.org/W3139999200","https://openalex.org/W4245178597","https://openalex.org/W4297562996","https://openalex.org/W6685433621","https://openalex.org/W6721792922","https://openalex.org/W7044433372"],"related_works":["https://openalex.org/W2013037783","https://openalex.org/W2909413202","https://openalex.org/W4385243142","https://openalex.org/W1999008563","https://openalex.org/W2561644314","https://openalex.org/W2912135124","https://openalex.org/W2794118724","https://openalex.org/W4206450104","https://openalex.org/W2883257033","https://openalex.org/W1564576805"],"abstract_inverted_index":{"Presilicon":[0],"forward":[1],"error":[2],"correction":[3],"(FEC)":[4],"decoding":[5],"hardware":[6,11,80],"is":[7,17,72,83,126,134],"typically":[8],"designed":[9],"using":[10,108],"description":[12],"languages":[13],"(HDLs).":[14],"Its":[15],"verification":[16,65,82,122],"a":[18,64,75,86,99,109],"hard":[19],"task":[20],"due":[21],"to":[22,26,57,105,112,131,136,152,167,171],"its":[23],"intrinsic":[24],"tendency":[25],"correct":[27],"errors.":[28],"The":[29,124,159],"generation":[30],"and":[31,78,103,119,144,170],"injection":[32],"of":[33,35,43,96,116,141],"millions":[34],"random":[36],"inputs":[37],"as":[38,40],"well":[39],"the":[41,44,69,79,106,114,121,138,142,154],"cross-checking":[42],"corresponding":[45],"outputs":[46],"are":[47,91],"highly":[48],"recommended.":[49],"Using":[50],"HDL":[51,168],"simulations":[52],"for":[53],"such":[54],"work":[55],"leads":[56],"prohibitive":[58],"execution":[59],"times.":[60],"This":[61],"letter":[62],"proposes":[63],"strategy":[66],"in":[67,93],"which":[68],"software":[70],"testbed":[71],"executed":[73],"on":[74,85],"multicore":[76],"host":[77,143],"under":[81],"prototyped":[84],"PCIe":[87,101,155],"accelerator":[88],"card.":[89],"Data":[90],"transferred":[92],"big":[94],"blocks":[95],"codewords":[97],"over":[98],"high-bandwidth":[100],"channel":[102],"applied":[104],"decoder":[107,125],"pipeline":[110],"management":[111],"maximize":[113],"use":[115],"computational":[117],"resources":[118],"minimize":[120],"time.":[123],"replicated":[127],"with":[128,147,165],"parallel":[129,139],"access":[130],"DDRs.":[132],"OpenMP":[133],"used":[135],"leverage":[137],"capabilities":[140],"OpenCL,":[145],"together":[146],"Xilinx":[148],"Runtime":[149],"(XRT)":[150],"Library,":[151],"manage":[153],"FPGA":[156],"card":[157],"execution.":[158],"results":[160],"show":[161],"an":[162],"important":[163],"speed-up":[164],"respect":[166],"simulation":[169],"other":[172],"prototyping":[173],"approaches.":[174]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2023-01-06T00:00:00"}
