{"id":"https://openalex.org/W3211095618","doi":"https://doi.org/10.1109/les.2021.3122395","title":"Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs","display_name":"Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs","publication_year":2021,"publication_date":"2021-10-25","ids":{"openalex":"https://openalex.org/W3211095618","doi":"https://doi.org/10.1109/les.2021.3122395","mag":"3211095618"},"language":"en","primary_location":{"id":"doi:10.1109/les.2021.3122395","is_oa":false,"landing_page_url":"https://doi.org/10.1109/les.2021.3122395","pdf_url":null,"source":{"id":"https://openalex.org/S22443479","display_name":"IEEE Embedded Systems Letters","issn_l":"1943-0663","issn":["1943-0663","1943-0671"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Embedded Systems Letters","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://digital.csic.es/bitstream/10261/336907/1/gatetftpost.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5058531522","display_name":"Ignacio M. Delgado-Lozano","orcid":"https://orcid.org/0000-0002-0003-3318"},"institutions":[{"id":"https://openalex.org/I166825849","display_name":"Tampere University","ror":"https://ror.org/033003e23","country_code":"FI","type":"education","lineage":["https://openalex.org/I166825849"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Ignacio M. Delgado-Lozano","raw_affiliation_strings":["Network and Information Security Group, Tampere University, Tampere, Finland"],"raw_orcid":"https://orcid.org/0000-0002-0003-3318","affiliations":[{"raw_affiliation_string":"Network and Information Security Group, Tampere University, Tampere, Finland","institution_ids":["https://openalex.org/I166825849"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043725292","display_name":"Erica Tena\u2010S\u00e1nchez","orcid":"https://orcid.org/0000-0002-8905-5715"},"institutions":[{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]},{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Erica Tena-Sanchez","raw_affiliation_strings":["Instituto de Microelectrónica de Sevilla (IMSE-CNM) (joint research centre by Universidad de Sevilla and CSIC), Seville, Spain"],"raw_orcid":"https://orcid.org/0000-0002-8905-5715","affiliations":[{"raw_affiliation_string":"Instituto de Microelectrónica de Sevilla (IMSE-CNM) (joint research centre by Universidad de Sevilla and CSIC), Seville, Spain","institution_ids":["https://openalex.org/I4210104545","https://openalex.org/I79238269"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101455624","display_name":"Juan N\u00fa\u00f1ez","orcid":"https://orcid.org/0000-0002-0279-9472"},"institutions":[{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]},{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Juan Nunez","raw_affiliation_strings":["Instituto de Microelectrónica de Sevilla (IMSE-CNM) (joint research centre by Universidad de Sevilla and CSIC), Seville, Spain"],"raw_orcid":"https://orcid.org/0000-0002-0279-9472","affiliations":[{"raw_affiliation_string":"Instituto de Microelectrónica de Sevilla (IMSE-CNM) (joint research centre by Universidad de Sevilla and CSIC), Seville, Spain","institution_ids":["https://openalex.org/I4210104545","https://openalex.org/I79238269"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073626271","display_name":"Antonio J. Acosta","orcid":"https://orcid.org/0000-0002-7934-9162"},"institutions":[{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]},{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Antonio J. Acosta","raw_affiliation_strings":["Instituto de Microelectrónica de Sevilla (IMSE-CNM) (joint research centre by Universidad de Sevilla and CSIC), Seville, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto de Microelectrónica de Sevilla (IMSE-CNM) (joint research centre by Universidad de Sevilla and CSIC), Seville, Spain","institution_ids":["https://openalex.org/I4210104545","https://openalex.org/I79238269"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.1608,"has_fulltext":true,"cited_by_count":2,"citation_normalized_percentile":{"value":0.45600273,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"14","issue":"2","first_page":"99","last_page":"102"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7793155908584595},{"id":"https://openalex.org/keywords/block-cipher","display_name":"Block cipher","score":0.5956641435623169},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5417384505271912},{"id":"https://openalex.org/keywords/side-channel-attack","display_name":"Side channel attack","score":0.49261337518692017},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.4337528347969055},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.42810332775115967},{"id":"https://openalex.org/keywords/power-analysis","display_name":"Power analysis","score":0.4268399477005005},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3761971592903137},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.36299896240234375},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.34798985719680786},{"id":"https://openalex.org/keywords/cryptography","display_name":"Cryptography","score":0.3118343949317932},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3033987283706665},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.17711538076400757},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1104215681552887}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7793155908584595},{"id":"https://openalex.org/C106544461","wikidata":"https://www.wikidata.org/wiki/Q543151","display_name":"Block cipher","level":3,"score":0.5956641435623169},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5417384505271912},{"id":"https://openalex.org/C49289754","wikidata":"https://www.wikidata.org/wiki/Q2267081","display_name":"Side channel attack","level":3,"score":0.49261337518692017},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.4337528347969055},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.42810332775115967},{"id":"https://openalex.org/C71743495","wikidata":"https://www.wikidata.org/wiki/Q2845210","display_name":"Power analysis","level":3,"score":0.4268399477005005},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3761971592903137},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.36299896240234375},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.34798985719680786},{"id":"https://openalex.org/C178489894","wikidata":"https://www.wikidata.org/wiki/Q8789","display_name":"Cryptography","level":2,"score":0.3118343949317932},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3033987283706665},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.17711538076400757},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1104215681552887},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/les.2021.3122395","is_oa":false,"landing_page_url":"https://doi.org/10.1109/les.2021.3122395","pdf_url":null,"source":{"id":"https://openalex.org/S22443479","display_name":"IEEE Embedded Systems Letters","issn_l":"1943-0663","issn":["1943-0663","1943-0671"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Embedded Systems Letters","raw_type":"journal-article"},{"id":"pmh:oai:digital.csic.es:10261/336907","is_oa":true,"landing_page_url":"http://hdl.handle.net/10261/336907","pdf_url":"https://digital.csic.es/bitstream/10261/336907/1/gatetftpost.pdf","source":{"id":"https://openalex.org/S4306400616","display_name":"DIGITAL.CSIC (Spanish National Research Council (CSIC))","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I134820265","host_organization_name":"Consejo Superior de Investigaciones Cient\u00edficas","host_organization_lineage":["https://openalex.org/I134820265"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"art\u00edculo"},{"id":"pmh:oai:idus.us.es:11441/127021","is_oa":true,"landing_page_url":"https://idus.us.es/handle//11441/127021","pdf_url":null,"source":{"id":"https://openalex.org/S4306400333","display_name":"idUS (Universidad de Sevilla)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79238269","host_organization_name":"Universidad de Sevilla","host_organization_lineage":["https://openalex.org/I79238269"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"},{"id":"pmh:oai:trepo.tuni.fi:10024/220934","is_oa":false,"landing_page_url":"https://trepo.tuni.fi/handle/10024/220934","pdf_url":null,"source":{"id":"https://openalex.org/S4306401860","display_name":"Tampere University Institutional Repository (Tampere University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I150589677","host_organization_name":"Tampere University of Applied Sciences","host_organization_lineage":["https://openalex.org/I150589677"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"acceptedVersion"}],"best_oa_location":{"id":"pmh:oai:digital.csic.es:10261/336907","is_oa":true,"landing_page_url":"http://hdl.handle.net/10261/336907","pdf_url":"https://digital.csic.es/bitstream/10261/336907/1/gatetftpost.pdf","source":{"id":"https://openalex.org/S4306400616","display_name":"DIGITAL.CSIC (Spanish National Research Council (CSIC))","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I134820265","host_organization_name":"Consejo Superior de Investigaciones Cient\u00edficas","host_organization_lineage":["https://openalex.org/I134820265"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"art\u00edculo"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G1635010105","display_name":"SECURE PLATFORM FOR ICT SYSTEMS ROOTED AT THE SILICON MANUFACTURING PROCESS","funder_award_id":"952622","funder_id":"https://openalex.org/F4320320300","funder_display_name":"European Commission"},{"id":"https://openalex.org/G3957910971","display_name":null,"funder_award_id":"804476","funder_id":"https://openalex.org/F4320320300","funder_display_name":"European Commission"},{"id":"https://openalex.org/G6870533126","display_name":null,"funder_award_id":"2014-2020","funder_id":"https://openalex.org/F4320320300","funder_display_name":"European Commission"}],"funders":[{"id":"https://openalex.org/F4320320300","display_name":"European Commission","ror":"https://ror.org/00k4n6c32"},{"id":"https://openalex.org/F4320326754","display_name":"Junta de Andaluc\u00eda","ror":"https://ror.org/01jem9c82"}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W3211095618.pdf","grobid_xml":"https://content.openalex.org/works/W3211095618.grobid-xml"},"referenced_works_count":25,"referenced_works":["https://openalex.org/W17122945","https://openalex.org/W1522953023","https://openalex.org/W1602420333","https://openalex.org/W1607006990","https://openalex.org/W2032197740","https://openalex.org/W2040475153","https://openalex.org/W2042035753","https://openalex.org/W2062632887","https://openalex.org/W2064769135","https://openalex.org/W2076432462","https://openalex.org/W2091604856","https://openalex.org/W2135522842","https://openalex.org/W2154909745","https://openalex.org/W2166807335","https://openalex.org/W2343807391","https://openalex.org/W2533098220","https://openalex.org/W2609486476","https://openalex.org/W2752504135","https://openalex.org/W2752505044","https://openalex.org/W3026655801","https://openalex.org/W4230627011","https://openalex.org/W4240560709","https://openalex.org/W4248033008","https://openalex.org/W6635937959","https://openalex.org/W6736893009"],"related_works":["https://openalex.org/W5280335","https://openalex.org/W4384807855","https://openalex.org/W2164725015","https://openalex.org/W4323926098","https://openalex.org/W2022533428","https://openalex.org/W2013165531","https://openalex.org/W182679101","https://openalex.org/W1968560271","https://openalex.org/W2081998479","https://openalex.org/W2043669269"],"abstract_inverted_index":{"The":[0,82],"design":[1,34,66],"of":[2,35,51,67,77,84,100,132],"secure":[3,23,133],"circuits":[4,134],"in":[5,58,95,108,121,129],"emerging":[6],"technologies":[7],"is":[8,125],"an":[9,19],"appealing":[10],"area":[11],"that":[12],"requires":[13],"new":[14],"efforts":[15],"and":[16,111],"attention":[17],"as":[18],"effective":[20],"solution":[21],"to":[22,64,117],"applications":[24],"with":[25,31,135],"power":[26,37,112],"constraints.":[27],"This":[28],"letter":[29],"deals":[30],"the":[32,65,68,73,78,89,130],"optimized":[33,105],"differential":[36],"analysis":[38],"(DPA)-resilient":[39],"hiding-based":[40],"techniques,":[41],"using":[42],"tunnel":[43],"field-effect":[44],"transistors":[45],"(TFETs).":[46],"Specifically,":[47],"proposed":[48],"TFET":[49,109],"implementations":[50],"dual-precharge-logic":[52],"primitives":[53],"optimizing":[54],"their":[55,118],"computation":[56,106],"tree":[57],"three":[59],"different":[60],"ways":[61],"are":[62],"applied":[63],"PRIDE":[69,79],"4-bit":[70],"substitution":[71],"box,":[72],"most":[74],"vulnerable":[75],"block":[76],"lightweight":[80],"cipher.":[81],"performance":[83],"simulation-based":[85],"DPA":[86],"attacks":[87,102],"on":[88],"proposals":[90],"has":[91],"shown":[92],"spectacular":[93],"results":[94],"security":[96],"gain":[97],"(34":[98],"out":[99],"48":[101],"fail":[103],"for":[104],"trees":[107],"technology)":[110],"reduction":[113],"($\\times":[114],"25$),":[115],"compared":[116],"CMOS-based":[119],"counterparts":[120],"65":[122],"nm,":[123],"which":[124],"a":[126],"significant":[127],"advance":[128],"development":[131],"TFETs.":[136]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1}],"updated_date":"2026-07-30T17:31:21.811387","created_date":"2025-10-10T00:00:00"}