{"id":"https://openalex.org/W2079326006","doi":"https://doi.org/10.1109/les.2014.2354454","title":"A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors","display_name":"A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors","publication_year":2014,"publication_date":"2014-09-08","ids":{"openalex":"https://openalex.org/W2079326006","doi":"https://doi.org/10.1109/les.2014.2354454","mag":"2079326006"},"language":"en","primary_location":{"id":"doi:10.1109/les.2014.2354454","is_oa":false,"landing_page_url":"https://doi.org/10.1109/les.2014.2354454","pdf_url":null,"source":{"id":"https://openalex.org/S22443479","display_name":"IEEE Embedded Systems Letters","issn_l":"1943-0663","issn":["1943-0663","1943-0671"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Embedded Systems Letters","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://porto.polito.it/2577336/2/papero.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5026016005","display_name":"Maurizio Martina","orcid":"https://orcid.org/0000-0002-3069-0319"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Maurizio Martina","raw_affiliation_strings":["Electronics and Telecommunications Department, Politecnico di Torino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Electronics and Telecommunications Department, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085812448","display_name":"Carlo Condo","orcid":"https://orcid.org/0000-0002-3050-036X"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Carlo Condo","raw_affiliation_strings":["Electronics and Telecommunications Department, Politecnico di Torino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Electronics and Telecommunications Department, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074150684","display_name":"Guido Masera","orcid":"https://orcid.org/0000-0003-2238-9443"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Guido Masera","raw_affiliation_strings":["Electronics and Telecommunications Department, Politecnico di Torino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Electronics and Telecommunications Department, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5077512098","display_name":"Maurizio Zamboni","orcid":"https://orcid.org/0000-0001-8179-5973"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Maurizio Zamboni","raw_affiliation_strings":["Electronics and Telecommunications Department, Politecnico di Torino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Electronics and Telecommunications Department, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5026016005"],"corresponding_institution_ids":["https://openalex.org/I177477856"],"apc_list":null,"apc_paid":null,"fwci":0.3584,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.68219281,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"6","issue":"4","first_page":"77","last_page":"80"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11321","display_name":"Error Correcting Code Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8139948844909668},{"id":"https://openalex.org/keywords/low-density-parity-check-code","display_name":"Low-density parity-check code","score":0.7259786128997803},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.7198086977005005},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6759492754936218},{"id":"https://openalex.org/keywords/error-detection-and-correction","display_name":"Error detection and correction","score":0.5027620792388916},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5001668930053711},{"id":"https://openalex.org/keywords/flash-memory","display_name":"Flash memory","score":0.4777790307998657},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.4626394808292389},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.46173226833343506},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.45790573954582214},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.44913944602012634},{"id":"https://openalex.org/keywords/flash","display_name":"Flash (photography)","score":0.43922486901283264},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.43394118547439575},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.4141327738761902},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.2550654411315918},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.20517238974571228}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8139948844909668},{"id":"https://openalex.org/C67692717","wikidata":"https://www.wikidata.org/wiki/Q187444","display_name":"Low-density parity-check code","level":3,"score":0.7259786128997803},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.7198086977005005},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6759492754936218},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.5027620792388916},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5001668930053711},{"id":"https://openalex.org/C2776531357","wikidata":"https://www.wikidata.org/wiki/Q174077","display_name":"Flash memory","level":2,"score":0.4777790307998657},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.4626394808292389},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.46173226833343506},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.45790573954582214},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.44913944602012634},{"id":"https://openalex.org/C2777526259","wikidata":"https://www.wikidata.org/wiki/Q221836","display_name":"Flash (photography)","level":2,"score":0.43922486901283264},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.43394118547439575},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.4141327738761902},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2550654411315918},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.20517238974571228},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/les.2014.2354454","is_oa":false,"landing_page_url":"https://doi.org/10.1109/les.2014.2354454","pdf_url":null,"source":{"id":"https://openalex.org/S22443479","display_name":"IEEE Embedded Systems Letters","issn_l":"1943-0663","issn":["1943-0663","1943-0671"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Embedded Systems Letters","raw_type":"journal-article"},{"id":"pmh:oai:porto.polito.it:2577336","is_oa":true,"landing_page_url":"http://porto.polito.it/2577336/2/papero.pdf","pdf_url":null,"source":{"id":"https://openalex.org/S4306402038","display_name":"PORTO Publications Open Repository TOrino (Politecnico di Torino)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I177477856","host_organization_name":"Politecnico di Torino","host_organization_lineage":["https://openalex.org/I177477856"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"ISSN:1943-0663","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":{"id":"pmh:oai:porto.polito.it:2577336","is_oa":true,"landing_page_url":"http://porto.polito.it/2577336/2/papero.pdf","pdf_url":null,"source":{"id":"https://openalex.org/S4306402038","display_name":"PORTO Publications Open Repository TOrino (Politecnico di Torino)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I177477856","host_organization_name":"Politecnico di Torino","host_organization_lineage":["https://openalex.org/I177477856"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"ISSN:1943-0663","raw_type":"info:eu-repo/semantics/article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W2032791864","https://openalex.org/W2048185145","https://openalex.org/W2075026597","https://openalex.org/W2097471282","https://openalex.org/W2103389232","https://openalex.org/W2108660906","https://openalex.org/W2115165154","https://openalex.org/W2118764568","https://openalex.org/W2135975985","https://openalex.org/W2140024209","https://openalex.org/W2149736242","https://openalex.org/W2161441594","https://openalex.org/W2179360174"],"related_works":["https://openalex.org/W2537420636","https://openalex.org/W2086578073","https://openalex.org/W2036350002","https://openalex.org/W2024706980","https://openalex.org/W2076885774","https://openalex.org/W2970146629","https://openalex.org/W1969077618","https://openalex.org/W1903254700","https://openalex.org/W3208164369","https://openalex.org/W2168336393"],"abstract_inverted_index":{"Reconfigurable":[0],"embedded":[1],"systems":[2],"can":[3,149],"take":[4],"advantage":[5],"of":[6,31,34,78,125,134,142],"programmable":[7],"devices,":[8],"such":[9,40],"as":[10,41,152,154],"microprocessors":[11],"and":[12,21,103,111,127],"field-programmable":[13],"gate":[14],"arrays":[15],"(FPGAs),":[16],"to":[17,24,74,91,106,121,140],"achieve":[18,107,150],"high":[19,48],"performance":[20,133],"flexibility.":[22],"Support":[23],"flexibility":[25],"often":[26],"comes":[27],"at":[28],"the":[29,76,122,131,135,143,146],"expense":[30],"large":[32],"amounts":[33],"nonvolatile":[35,38],"memories.":[36],"Unfortunately,":[37],"memories,":[39],"multilevel-cell":[42],"(MLC)":[43],"NAND":[44,80],"flash,":[45],"exhibit":[46],"a":[47,93,99],"raw":[49],"bit":[50],"error":[51,61],"rate":[52],"that":[53,67],"is":[54,118],"mitigated":[55],"by":[56],"employing":[57],"different":[58],"techniques,":[59],"including":[60],"correcting":[62],"codes.":[63],"Recent":[64],"results":[65,129],"show":[66,130],"low-density-parity-check":[68],"(LDPC)":[69],"codes":[70],"are":[71],"good":[72],"candidates":[73],"improve":[75],"reliability":[77],"MLC":[79],"flash":[81],"memories":[82],"especially":[83],"when":[84],"page":[85],"size":[86],"increases.":[87],"This":[88],"letter":[89],"proposes":[90],"use":[92],"joint":[94],"source/channel":[95],"approach,":[96],"based":[97],"on":[98],"modified":[100],"arithmetic":[101],"code":[102],"LDPC":[104],"codes,":[105],"both":[108],"data":[109,124],"compression":[110],"improved":[112],"system":[113,137,148],"reliability.":[114],"The":[115],"proposed":[116,136,147],"technique":[117],"then":[119],"applied":[120],"configuration":[123],"FPGAs":[126],"experimental":[128],"superior":[132],"with":[138],"respect":[139],"state":[141],"art.":[144],"Indeed,":[145],"bit-error-rates":[151],"low":[153],"about":[155],"10":[156],"<sup":[157],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[158],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">-8</sup>":[159],"for":[160],"cell-to-cell":[161],"coupling":[162],"strength":[163],"factors":[164],"well":[165],"higher":[166],"than":[167],"1.0.":[168]},"counts_by_year":[{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
