{"id":"https://openalex.org/W2124495571","doi":"https://doi.org/10.1109/les.2010.2044365","title":"An FPGA-Based Framework for Technology-Aware Prototyping of Multicore Embedded Architectures","display_name":"An FPGA-Based Framework for Technology-Aware Prototyping of Multicore Embedded Architectures","publication_year":2010,"publication_date":"2010-03-01","ids":{"openalex":"https://openalex.org/W2124495571","doi":"https://doi.org/10.1109/les.2010.2044365","mag":"2124495571"},"language":"en","primary_location":{"id":"doi:10.1109/les.2010.2044365","is_oa":false,"landing_page_url":"https://doi.org/10.1109/les.2010.2044365","pdf_url":null,"source":{"id":"https://openalex.org/S22443479","display_name":"IEEE Embedded Systems Letters","issn_l":"1943-0663","issn":["1943-0663","1943-0671"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Embedded Systems Letters","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050421874","display_name":"Paolo Meloni","orcid":"https://orcid.org/0000-0002-8106-4641"},"institutions":[{"id":"https://openalex.org/I172446870","display_name":"University of Cagliari","ror":"https://ror.org/003109y17","country_code":"IT","type":"education","lineage":["https://openalex.org/I172446870"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Paolo Meloni","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, University of Cagliari, Cagliari, Italy","Dept. of Electr. & Electron. Eng., Univ. of Cagliari, Cagliari, , Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, University of Cagliari, Cagliari, Italy","institution_ids":["https://openalex.org/I172446870"]},{"raw_affiliation_string":"Dept. of Electr. & Electron. Eng., Univ. of Cagliari, Cagliari, , Italy","institution_ids":["https://openalex.org/I172446870"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081406299","display_name":"Simone Secchi","orcid":"https://orcid.org/0000-0002-8539-1578"},"institutions":[{"id":"https://openalex.org/I172446870","display_name":"University of Cagliari","ror":"https://ror.org/003109y17","country_code":"IT","type":"education","lineage":["https://openalex.org/I172446870"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Simone Secchi","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, University of Cagliari, Cagliari, Italy","Dept. of Electr. & Electron. Eng., Univ. of Cagliari, Cagliari, , Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, University of Cagliari, Cagliari, Italy","institution_ids":["https://openalex.org/I172446870"]},{"raw_affiliation_string":"Dept. of Electr. & Electron. Eng., Univ. of Cagliari, Cagliari, , Italy","institution_ids":["https://openalex.org/I172446870"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5007761671","display_name":"Luigi Raffo","orcid":"https://orcid.org/0000-0001-9683-009X"},"institutions":[{"id":"https://openalex.org/I172446870","display_name":"University of Cagliari","ror":"https://ror.org/003109y17","country_code":"IT","type":"education","lineage":["https://openalex.org/I172446870"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luigi Raffo","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, University of Cagliari, Cagliari, Italy","Dept. of Electr. & Electron. Eng., Univ. of Cagliari, Cagliari, , Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, University of Cagliari, Cagliari, Italy","institution_ids":["https://openalex.org/I172446870"]},{"raw_affiliation_string":"Dept. of Electr. & Electron. Eng., Univ. of Cagliari, Cagliari, , Italy","institution_ids":["https://openalex.org/I172446870"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I172446870"],"apc_list":null,"apc_paid":null,"fwci":3.4931,"has_fulltext":false,"cited_by_count":20,"citation_normalized_percentile":{"value":0.93138187,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"2","issue":"1","first_page":"5","last_page":"9"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.834873378276825},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7787485718727112},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.7243345379829407},{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.7034545540809631},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.6228891015052795},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.6082818508148193},{"id":"https://openalex.org/keywords/hardware-emulation","display_name":"Hardware emulation","score":0.5690768361091614},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5569326877593994},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5439630746841431},{"id":"https://openalex.org/keywords/microblaze","display_name":"MicroBlaze","score":0.5168374180793762},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.4780198335647583},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.12717527151107788}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.834873378276825},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7787485718727112},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.7243345379829407},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.7034545540809631},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.6228891015052795},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.6082818508148193},{"id":"https://openalex.org/C94115699","wikidata":"https://www.wikidata.org/wiki/Q5656406","display_name":"Hardware emulation","level":3,"score":0.5690768361091614},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5569326877593994},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5439630746841431},{"id":"https://openalex.org/C2777575374","wikidata":"https://www.wikidata.org/wiki/Q1644704","display_name":"MicroBlaze","level":3,"score":0.5168374180793762},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.4780198335647583},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.12717527151107788},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/les.2010.2044365","is_oa":false,"landing_page_url":"https://doi.org/10.1109/les.2010.2044365","pdf_url":null,"source":{"id":"https://openalex.org/S22443479","display_name":"IEEE Embedded Systems Letters","issn_l":"1943-0663","issn":["1943-0663","1943-0671"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Embedded Systems Letters","raw_type":"journal-article"},{"id":"pmh:oai:iris.unica.it:11584/107669","is_oa":false,"landing_page_url":"http://hdl.handle.net/11584/107669","pdf_url":null,"source":{"id":"https://openalex.org/S4377196293","display_name":"UNICA IRIS Institutional Research Information System (University of Cagliari)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I172446870","host_organization_name":"University of Cagliari","host_organization_lineage":["https://openalex.org/I172446870"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W1481733864","https://openalex.org/W1861759238","https://openalex.org/W1936682962","https://openalex.org/W1970939331","https://openalex.org/W2003825844","https://openalex.org/W2039401562","https://openalex.org/W2062581063","https://openalex.org/W2072959483","https://openalex.org/W2108321287","https://openalex.org/W2120635877","https://openalex.org/W2121082877","https://openalex.org/W2121845498","https://openalex.org/W2121856707","https://openalex.org/W2128258670","https://openalex.org/W2145021036","https://openalex.org/W2155764480","https://openalex.org/W2156475585","https://openalex.org/W2164264749","https://openalex.org/W2171940713","https://openalex.org/W3137094666","https://openalex.org/W3151070926","https://openalex.org/W3151365514","https://openalex.org/W4238549726","https://openalex.org/W4251534053","https://openalex.org/W6829898806"],"related_works":["https://openalex.org/W2170071008","https://openalex.org/W2103996454","https://openalex.org/W3029775214","https://openalex.org/W2390650884","https://openalex.org/W2093057572","https://openalex.org/W2129151116","https://openalex.org/W2261632671","https://openalex.org/W2888526229","https://openalex.org/W119599369","https://openalex.org/W2966987601"],"abstract_inverted_index":{"The":[0,64],"use":[1],"of":[2,12,60,79,84,90,99,101,106,114],"cycle-accurate":[3,45],"software":[4],"simulators":[5],"as":[6,53,94,96],"a":[7,26,54,77,107],"foundation":[8],"for":[9,57,81],"the":[10,14,58,67,72,82,85,88,91,97,115],"exploration":[11,59],"all":[13],"possible":[15],"full-system":[16],"hardware-software":[17],"(hw-sw)":[18],"configurations":[19],"does":[20],"not":[21],"appear":[22],"to":[23,29,69],"be":[24],"anymore":[25],"feasible":[27],"way":[28],"handle":[30],"modern":[31],"embedded":[32],"multicore":[33,62],"systems":[34],"complexity.":[35],"In":[36],"this":[37],"letter,":[38],"an":[39],"field":[40],"programmable":[41],"gate":[42],"array":[43],"(FPGA)-based":[44],"hardware":[46],"emulation":[47],"framework":[48,65],"is":[49],"presented":[50],"and":[51,87,103],"proposed":[52],"research":[55],"accelerator":[56],"complete":[61],"systems.":[63],"provides":[66],"possibility":[68],"extract":[70],"from":[71],"automatically":[73],"instantiated":[74],"hardware-emulated":[75],"system":[76],"set":[78],"metrics":[80],"assessment":[83],"performance":[86],"evaluation":[89],"architectural":[92],"tradeoffs,":[93],"well":[95],"estimation":[98],"figures":[100],"power":[102],"area":[104],"consumption":[105],"prospective":[108],"application-specified":[109],"integrated":[110],"circuit":[111],"(ASIC)":[112],"implementation":[113],"considered":[116],"architecture.":[117]},"counts_by_year":[{"year":2023,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":7},{"year":2012,"cited_by_count":5}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
