{"id":"https://openalex.org/W2125532166","doi":"https://doi.org/10.1109/les.2009.2034711","title":"BOUNCE: A New High-Resolution Time-Interval Measurement Architecture","display_name":"BOUNCE: A New High-Resolution Time-Interval Measurement Architecture","publication_year":2009,"publication_date":"2009-08-01","ids":{"openalex":"https://openalex.org/W2125532166","doi":"https://doi.org/10.1109/les.2009.2034711","mag":"2125532166"},"language":"en","primary_location":{"id":"doi:10.1109/les.2009.2034711","is_oa":false,"landing_page_url":"https://doi.org/10.1109/les.2009.2034711","pdf_url":null,"source":{"id":"https://openalex.org/S22443479","display_name":"IEEE Embedded Systems Letters","issn_l":"1943-0663","issn":["1943-0663","1943-0671"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Embedded Systems Letters","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109624826","display_name":"R. Salomon","orcid":null},"institutions":[{"id":"https://openalex.org/I4665924","display_name":"University of Rostock","ror":"https://ror.org/03zdwsf69","country_code":"DE","type":"education","lineage":["https://openalex.org/I4665924"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"R. Salomon","raw_affiliation_strings":["Institute of Applied Microelectronics and Computer Science, University of Rostock, Rostock, Germany","Inst. of Appl. Microelectron. & Comput. Sci., Univ. of Rostock, Rostock, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Applied Microelectronics and Computer Science, University of Rostock, Rostock, Germany","institution_ids":["https://openalex.org/I4665924"]},{"raw_affiliation_string":"Inst. of Appl. Microelectron. & Comput. Sci., Univ. of Rostock, Rostock, Germany","institution_ids":["https://openalex.org/I4665924"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002899190","display_name":"Ralf Joost","orcid":null},"institutions":[{"id":"https://openalex.org/I4665924","display_name":"University of Rostock","ror":"https://ror.org/03zdwsf69","country_code":"DE","type":"education","lineage":["https://openalex.org/I4665924"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"R. Joost","raw_affiliation_strings":["Institute of Applied Microelectronics and Computer Science, University of Rostock, Rostock, Germany","Inst. of Appl. Microelectron. & Comput. Sci., Univ. of Rostock, Rostock, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Applied Microelectronics and Computer Science, University of Rostock, Rostock, Germany","institution_ids":["https://openalex.org/I4665924"]},{"raw_affiliation_string":"Inst. of Appl. Microelectron. & Comput. Sci., Univ. of Rostock, Rostock, Germany","institution_ids":["https://openalex.org/I4665924"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.831,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.86344768,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"1","issue":"2","first_page":"56","last_page":"59"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7457796931266785},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.5992611646652222},{"id":"https://openalex.org/keywords/stratix","display_name":"Stratix","score":0.5944831967353821},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5636754035949707},{"id":"https://openalex.org/keywords/interval","display_name":"Interval (graph theory)","score":0.47808003425598145},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.4754193425178528},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.4532108008861542},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4287911057472229},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.42287978529930115},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4183158278465271},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.4024907350540161},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3731849193572998},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.23243504762649536},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11884692311286926}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7457796931266785},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.5992611646652222},{"id":"https://openalex.org/C2776277307","wikidata":"https://www.wikidata.org/wiki/Q22074755","display_name":"Stratix","level":3,"score":0.5944831967353821},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5636754035949707},{"id":"https://openalex.org/C2778067643","wikidata":"https://www.wikidata.org/wiki/Q166507","display_name":"Interval (graph theory)","level":2,"score":0.47808003425598145},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.4754193425178528},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.4532108008861542},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4287911057472229},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.42287978529930115},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4183158278465271},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.4024907350540161},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3731849193572998},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.23243504762649536},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11884692311286926},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/les.2009.2034711","is_oa":false,"landing_page_url":"https://doi.org/10.1109/les.2009.2034711","pdf_url":null,"source":{"id":"https://openalex.org/S22443479","display_name":"IEEE Embedded Systems Letters","issn_l":"1943-0663","issn":["1943-0663","1943-0671"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Embedded Systems Letters","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/11","score":0.46000000834465027,"display_name":"Sustainable cities and communities"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W49964179","https://openalex.org/W1996874179","https://openalex.org/W2060921230","https://openalex.org/W2126008551","https://openalex.org/W2147196983","https://openalex.org/W2149552064","https://openalex.org/W2152443753","https://openalex.org/W2335804873","https://openalex.org/W4232143692"],"related_works":["https://openalex.org/W3015599398","https://openalex.org/W2188730438","https://openalex.org/W2157230896","https://openalex.org/W2792778858","https://openalex.org/W2034656493","https://openalex.org/W2144444173","https://openalex.org/W2014165129","https://openalex.org/W2362904186","https://openalex.org/W4309935840","https://openalex.org/W2114232017"],"abstract_inverted_index":{"Measuring":[0],"the":[1,43,50,65,70,74,78,82,89,94,109],"duration":[2],"of":[3,103,161],"a":[4,8,34,56,124],"time":[5,20,27,48,125],"interval":[6],"is":[7,16,136],"discretization":[9],"process":[10],"in":[11,63],"which":[12,64],"an":[13,115,152,162],"input":[14],"signal":[15,46],"sampled":[17],"at":[18],"discrete":[19],"steps.":[21],"Most":[22],"digital":[23],"systems":[24],"generate":[25],"these":[26,104],"steps":[28],"by":[29,69],"active":[30],"components,":[31],"such":[32],"as":[33,88,151,159],"generator,":[35],"flip-flops,":[36],"dedicated":[37],"delay":[38],"elements,":[39],"gates,":[40],"inverters,":[41],"and":[42,100,146],"like,":[44],"whose":[45],"propagation":[47],"determine":[49],"system's":[51],"resolution.":[52],"This":[53],"paper":[54],"presents":[55],"new":[57],"time-interval":[58],"measurement":[59],"architecture,":[60,134],"called":[61],"BOUNCE,":[62],"delays":[66],"are":[67,106],"realized":[68,150],"simplest":[71],"elements":[72,80],"possible:":[73],"(metal)":[75],"wires":[76],"between":[77],"logic":[79],"within":[81],"chip.":[83],"Standard":[84],"RS":[85],"latches":[86,105],"serve":[87],"sampling":[90],"units.":[91],"Even":[92],"though":[93],"requirements":[95],"with":[96],"respect":[97],"to":[98,132,139],"setup":[99],"hold":[101],"times":[102],"not":[107],"met,":[108],"architecture":[110],"operates":[111],"quite":[112],"reliably:":[113],"on":[114,142,155],"Altera":[116],"Stratix":[117],"II":[118],"field-programmable":[119,143],"gate":[120,144],"array,":[121],"BOUNCE":[122,135],"yields":[123],"resolution":[126],"better":[127],"than":[128],"4":[129],"ps.":[130],"Due":[131],"its":[133,156],"ideally":[137],"suited":[138],"be":[140,149],"implemented":[141],"arrays":[145],"can":[147],"thus":[148],"embedded":[153],"system":[154],"own":[157],"or":[158],"part":[160],"existing":[163],"one.":[164]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":3}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}