{"id":"https://openalex.org/W2077779718","doi":"https://doi.org/10.1109/lcn.2014.6925785","title":"MPFC: Massively Parallel Firewall Circuits","display_name":"MPFC: Massively Parallel Firewall Circuits","publication_year":2014,"publication_date":"2014-09-01","ids":{"openalex":"https://openalex.org/W2077779718","doi":"https://doi.org/10.1109/lcn.2014.6925785","mag":"2077779718"},"language":"en","primary_location":{"id":"doi:10.1109/lcn.2014.6925785","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lcn.2014.6925785","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"39th Annual IEEE Conference on Local Computer Networks","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5068733274","display_name":"Sven Hager","orcid":"https://orcid.org/0000-0003-0835-0112"},"institutions":[{"id":"https://openalex.org/I39343248","display_name":"Humboldt-Universit\u00e4t zu Berlin","ror":"https://ror.org/01hcx6992","country_code":"DE","type":"education","lineage":["https://openalex.org/I39343248"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Sven Hager","raw_affiliation_strings":["Computer Engineering Group, Humboldt University of Berlin, Germany"],"affiliations":[{"raw_affiliation_string":"Computer Engineering Group, Humboldt University of Berlin, Germany","institution_ids":["https://openalex.org/I39343248"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011103119","display_name":"Frank Winkler","orcid":"https://orcid.org/0000-0003-4892-6104"},"institutions":[{"id":"https://openalex.org/I39343248","display_name":"Humboldt-Universit\u00e4t zu Berlin","ror":"https://ror.org/01hcx6992","country_code":"DE","type":"education","lineage":["https://openalex.org/I39343248"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Frank Winkler","raw_affiliation_strings":["Computer Engineering Group, Humboldt University of Berlin, Germany"],"affiliations":[{"raw_affiliation_string":"Computer Engineering Group, Humboldt University of Berlin, Germany","institution_ids":["https://openalex.org/I39343248"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049715028","display_name":"Bj\u00f6rn Scheuermann","orcid":"https://orcid.org/0000-0002-1133-1775"},"institutions":[{"id":"https://openalex.org/I39343248","display_name":"Humboldt-Universit\u00e4t zu Berlin","ror":"https://ror.org/01hcx6992","country_code":"DE","type":"education","lineage":["https://openalex.org/I39343248"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Bjorn Scheuermann","raw_affiliation_strings":["Computer Engineering Group, Humboldt University of Berlin, Germany"],"affiliations":[{"raw_affiliation_string":"Computer Engineering Group, Humboldt University of Berlin, Germany","institution_ids":["https://openalex.org/I39343248"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081549293","display_name":"Klaus Reinhardt","orcid":"https://orcid.org/0000-0001-7200-4594"},"institutions":[{"id":"https://openalex.org/I39343248","display_name":"Humboldt-Universit\u00e4t zu Berlin","ror":"https://ror.org/01hcx6992","country_code":"DE","type":"education","lineage":["https://openalex.org/I39343248"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Klaus Reinhardt","raw_affiliation_strings":["Computer Engineering Group, Humboldt University of Berlin, Germany"],"affiliations":[{"raw_affiliation_string":"Computer Engineering Group, Humboldt University of Berlin, Germany","institution_ids":["https://openalex.org/I39343248"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5068733274"],"corresponding_institution_ids":["https://openalex.org/I39343248"],"apc_list":null,"apc_paid":null,"fwci":2.4518,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.8945361,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"19","issue":null,"first_page":"305","last_page":"313"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10400","display_name":"Network Security and Intrusion Detection","score":0.9883999824523926,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10714","display_name":"Software-Defined Networks and 5G","score":0.9782000184059143,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7889999151229858},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6311397552490234},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.5628641247749329},{"id":"https://openalex.org/keywords/header","display_name":"Header","score":0.5610290169715881},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.5220530033111572},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5090270042419434},{"id":"https://openalex.org/keywords/massively-parallel","display_name":"Massively parallel","score":0.504167914390564},{"id":"https://openalex.org/keywords/firewall","display_name":"Firewall (physics)","score":0.45781224966049194},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.43365517258644104},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.4275517165660858},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3946765959262848},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.36900195479393005},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.36782607436180115},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.12417304515838623},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09920817613601685},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.07870015501976013}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7889999151229858},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6311397552490234},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.5628641247749329},{"id":"https://openalex.org/C48105269","wikidata":"https://www.wikidata.org/wiki/Q1141160","display_name":"Header","level":2,"score":0.5610290169715881},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.5220530033111572},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5090270042419434},{"id":"https://openalex.org/C190475519","wikidata":"https://www.wikidata.org/wiki/Q544384","display_name":"Massively parallel","level":2,"score":0.504167914390564},{"id":"https://openalex.org/C77714075","wikidata":"https://www.wikidata.org/wiki/Q5452017","display_name":"Firewall (physics)","level":5,"score":0.45781224966049194},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.43365517258644104},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.4275517165660858},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3946765959262848},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.36900195479393005},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36782607436180115},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.12417304515838623},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09920817613601685},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.07870015501976013},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C183915046","wikidata":"https://www.wikidata.org/wiki/Q1316152","display_name":"Charged black hole","level":4,"score":0.0},{"id":"https://openalex.org/C115304011","wikidata":"https://www.wikidata.org/wiki/Q72755","display_name":"Schwarzschild radius","level":3,"score":0.0},{"id":"https://openalex.org/C74650414","wikidata":"https://www.wikidata.org/wiki/Q11397","display_name":"Classical mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C124017977","wikidata":"https://www.wikidata.org/wiki/Q11412","display_name":"Gravitation","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/lcn.2014.6925785","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lcn.2014.6925785","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"39th Annual IEEE Conference on Local Computer Networks","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W79029001","https://openalex.org/W1590238182","https://openalex.org/W1597405022","https://openalex.org/W1887496082","https://openalex.org/W1975959118","https://openalex.org/W1992811742","https://openalex.org/W2018903351","https://openalex.org/W2019461336","https://openalex.org/W2030224590","https://openalex.org/W2064584332","https://openalex.org/W2077688755","https://openalex.org/W2103189753","https://openalex.org/W2108084305","https://openalex.org/W2109752950","https://openalex.org/W2134519279","https://openalex.org/W2137145600","https://openalex.org/W2139587756","https://openalex.org/W2143377393","https://openalex.org/W2151553380","https://openalex.org/W2157085439","https://openalex.org/W2164905748","https://openalex.org/W3139681473","https://openalex.org/W6635317570","https://openalex.org/W6648603970"],"related_works":["https://openalex.org/W2171597999","https://openalex.org/W2189136227","https://openalex.org/W1866537546","https://openalex.org/W630850086","https://openalex.org/W3200508093","https://openalex.org/W4372053344","https://openalex.org/W3193978431","https://openalex.org/W2379752180","https://openalex.org/W2519240373","https://openalex.org/W2111408175"],"abstract_inverted_index":{"The":[0,110],"process":[1],"of":[2,7,13,20,103,119,135],"matching":[3],"the":[4,31,64,68,101],"header":[5],"fields":[6],"network":[8],"packets":[9],"against":[10],"a":[11,16,59,93,116],"set":[12],"rules":[14],"is":[15,42,47],"performance":[17],"critical":[18],"task":[19],"firewalls.":[21],"Software-based":[22],"solutions":[23],"have":[24],"no":[25],"chance":[26],"to":[27,51,54,58,67,95],"keep":[28],"pace":[29],"with":[30],"ever-growing":[32],"data":[33],"rates":[34],"in":[35,49,87,100,143],"high-speed":[36],"networks.":[37],"However,":[38],"specialized":[39],"filtering":[40],"hardware":[41],"costly":[43],"because":[44],"complex":[45],"logic":[46,66],"required":[48],"order":[50],"be":[52,126],"able":[53],"apply":[55],"arbitrary":[56],"rulesets":[57],"packet":[60,121],"stream.":[61],"By":[62],"adapting":[63],"implemented":[65],"specific":[69],"firewall":[70,98],"ruleset,":[71],"FPGAs":[72],"allow":[73],"for":[74,107],"much":[75],"more":[76,81],"specifically":[77],"tailored":[78],"and":[79,132],"thus":[80],"efficient":[82],"processing":[83,138],"than":[84,140],"ruleset-independent":[85],"circuits":[86,99,114],"an":[88],"ASIC.":[89],"We":[90],"present":[91],"MPFC,":[92],"method":[94],"generate":[96],"customized":[97],"form":[102],"synthesizable":[104],"VHDL":[105],"code":[106],"FPGA":[108],"configuration.":[109],"highly":[111],"parallel":[112],"MPFC":[113],"achieve":[115],"deterministic":[117],"throughput":[118],"one":[120],"per":[122],"clock":[123,130],"cycle,":[124],"can":[125],"operated":[127],"at":[128],"high":[129],"frequencies,":[131],"provide":[133],"orders":[134],"magnitudes":[136],"shorter":[137],"latencies":[139],"previous":[141],"work":[142],"this":[144],"direction.":[145]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}