{"id":"https://openalex.org/W7140091590","doi":"https://doi.org/10.1109/lca.2026.3676988","title":"Capacity-Latency Tradeoffs in CXL Memory Expander at Hyperscale","display_name":"Capacity-Latency Tradeoffs in CXL Memory Expander at Hyperscale","publication_year":2026,"publication_date":"2026-01-01","ids":{"openalex":"https://openalex.org/W7140091590","doi":"https://doi.org/10.1109/lca.2026.3676988"},"language":null,"primary_location":{"id":"doi:10.1109/lca.2026.3676988","is_oa":true,"landing_page_url":"https://doi.org/10.1109/lca.2026.3676988","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Architecture Letters","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://doi.org/10.1109/lca.2026.3676988","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088582502","display_name":"Haneul Park","orcid":"https://orcid.org/0009-0006-6286-0980"},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Haneul Park","raw_affiliation_strings":["University of Illinois Urbana-Champaign, Urbana, IL, USA"],"raw_orcid":"https://orcid.org/0009-0006-6286-0980","affiliations":[{"raw_affiliation_string":"University of Illinois Urbana-Champaign, Urbana, IL, USA","institution_ids":["https://openalex.org/I157725225"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057534738","display_name":"Grant Ayers","orcid":null},"institutions":[{"id":"https://openalex.org/I1291425158","display_name":"Google (United States)","ror":"https://ror.org/00njsd438","country_code":"US","type":"company","lineage":["https://openalex.org/I1291425158","https://openalex.org/I4210128969"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Grant Ayers","raw_affiliation_strings":["Google LLC, Mountain View, CA, USA"],"raw_orcid":"https://orcid.org/0000-0002-7990-9780","affiliations":[{"raw_affiliation_string":"Google LLC, Mountain View, CA, USA","institution_ids":["https://openalex.org/I1291425158"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037648751","display_name":"Nam Sung Kim","orcid":"https://orcid.org/0000-0002-0442-5634"},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nam Sung Kim","raw_affiliation_strings":["University of Illinois Urbana-Champaign, Urbana, IL, USA"],"raw_orcid":"https://orcid.org/0000-0002-0442-5634","affiliations":[{"raw_affiliation_string":"University of Illinois Urbana-Champaign, Urbana, IL, USA","institution_ids":["https://openalex.org/I157725225"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060306684","display_name":"Philip Levis","orcid":"https://orcid.org/0000-0003-2934-2701"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Philip Levis","raw_affiliation_strings":["Stanford University, Stanford, CA, USA"],"raw_orcid":"https://orcid.org/0000-0003-2934-2701","affiliations":[{"raw_affiliation_string":"Stanford University, Stanford, CA, USA","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101549909","display_name":"Brian Morris","orcid":null},"institutions":[{"id":"https://openalex.org/I1291425158","display_name":"Google (United States)","ror":"https://ror.org/00njsd438","country_code":"US","type":"company","lineage":["https://openalex.org/I1291425158","https://openalex.org/I4210128969"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Brian Morris","raw_affiliation_strings":["Google LLC, Mountain View, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Google LLC, Mountain View, CA, USA","institution_ids":["https://openalex.org/I1291425158"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5088582502"],"corresponding_institution_ids":["https://openalex.org/I157725225"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.71069026,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"25","issue":"1","first_page":"122","last_page":"125"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.8033000230789185,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.8033000230789185,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.07639999687671661,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.013899999670684338,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.43140000104904175},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.37630000710487366},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.34450000524520874}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7361999750137329},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.43140000104904175},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.37630000710487366},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.34450000524520874},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.32499998807907104},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3052000105381012},{"id":"https://openalex.org/C199639397","wikidata":"https://www.wikidata.org/wiki/Q1788588","display_name":"Engineering drawing","level":1,"score":0.26840001344680786},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2556000053882599},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.2533000111579895},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.23999999463558197}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/lca.2026.3676988","is_oa":true,"landing_page_url":"https://doi.org/10.1109/lca.2026.3676988","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Architecture Letters","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1109/lca.2026.3676988","is_oa":true,"landing_page_url":"https://doi.org/10.1109/lca.2026.3676988","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Architecture Letters","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306087","display_name":"Semiconductor Research Corporation","ror":"https://ror.org/047z4n946"},{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"DRAM":[0,34,169],"dominates":[1],"the":[2,49,63,67,85,92,95,112,119,166,174],"cost":[3,43],"of":[4,59,97,122],"hyperscale":[5],"datacenter":[6],"servers":[7],"today":[8],"and":[9,66,78,94,107,118,137],"AI-driven":[10],"memory":[11,20,61,86,124],"supply":[12],"shortages":[13],"are":[14,22],"pushing":[15],"costs":[16,29],"even":[17],"higher.":[18],"CXL":[19],"expanders":[21,40],"a":[23,60,108,115,127,133,157],"new":[24],"technology":[25],"to":[26,91],"reduce":[27,148],"server":[28],"by":[30],"reusing":[31],"legacy":[32],"DDR":[33],"modules":[35],"from":[36,126],"older":[37],"servers.":[38],"Memory":[39],"further":[41],"save":[42],"through":[44],"inline":[45],"compression":[46,64,68,106,135,161],"that":[47,80,131],"increases":[48],"effective":[50],"capacity.":[51],"This":[52],"paper":[53],"investigates":[54],"two":[55],"critical":[56],"design":[57,72],"points":[58,73],"expander:":[62],"algorithm":[65,136,162],"block":[69,110,138],"size.":[70],"Both":[71],"introduce":[74],"tradeoffs":[75],"between":[76],"latency":[77,164],"capacity":[79,144],"involve":[81],"complex":[82,160],"interactions":[83],"with":[84],"expander":[87,143],"architecture,":[88],"access":[89,149],"patterns":[90],"device,":[93],"entropy":[96],"stored":[98],"data.":[99],"Current":[100],"commercial":[101],"devices":[102],"use":[103],"simple,":[104],"fast":[105],"4kB":[109],"as":[111],"default.":[113],"Using":[114],"compressibility":[116],"benchmark":[117],"latest":[120],"traces":[121],"cold":[123],"accesses":[125],"hyperscaler,":[128],"we":[129],"find":[130],"using":[132,156],"different":[134],"size":[139],"can":[140],"simultaneously":[141],"increase":[142],"<italic":[145],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[146],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">and</i>":[147],"latency.":[150],"The":[151],"key":[152],"insight":[153],"is":[154],"counter-intuitive:":[155],"slower,":[158],"more":[159,171],"improves":[163],"because":[165],"reduction":[167],"in":[168],"traffic":[170],"than":[172],"offsets":[173],"additional":[175],"decompression":[176],"time.":[177]},"counts_by_year":[],"updated_date":"2026-04-09T06:08:40.794217","created_date":"2026-03-24T00:00:00"}
