{"id":"https://openalex.org/W7135080350","doi":"https://doi.org/10.1109/lca.2026.3673181","title":"CXL-Tracer: Accurate, Full-System Memory Tracing on Commercial Hardware via CXL Memory","display_name":"CXL-Tracer: Accurate, Full-System Memory Tracing on Commercial Hardware via CXL Memory","publication_year":2026,"publication_date":"2026-01-01","ids":{"openalex":"https://openalex.org/W7135080350","doi":"https://doi.org/10.1109/lca.2026.3673181"},"language":null,"primary_location":{"id":"doi:10.1109/lca.2026.3673181","is_oa":true,"landing_page_url":"https://doi.org/10.1109/lca.2026.3673181","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Architecture Letters","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://doi.org/10.1109/lca.2026.3673181","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000862490","display_name":"Srikar Vanavasam","orcid":"https://orcid.org/0000-0002-4224-2812"},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Srikar Vanavasam","raw_affiliation_strings":["University of Illinois Urbana-Champaign, Urbana, IL, USA"],"raw_orcid":"https://orcid.org/0000-0002-4224-2812","affiliations":[{"raw_affiliation_string":"University of Illinois Urbana-Champaign, Urbana, IL, USA","institution_ids":["https://openalex.org/I157725225"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5128079325","display_name":"Austin Antony Cruz","orcid":null},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Austin Antony Cruz","raw_affiliation_strings":["University of Illinois Urbana-Champaign, Urbana, IL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Illinois Urbana-Champaign, Urbana, IL, USA","institution_ids":["https://openalex.org/I157725225"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5037648751","display_name":"Nam Sung Kim","orcid":"https://orcid.org/0000-0002-0442-5634"},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nam Sung Kim","raw_affiliation_strings":["University of Illinois Urbana-Champaign, Urbana, IL, USA"],"raw_orcid":"https://orcid.org/0000-0002-0442-5634","affiliations":[{"raw_affiliation_string":"University of Illinois Urbana-Champaign, Urbana, IL, USA","institution_ids":["https://openalex.org/I157725225"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I157725225"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.24397736,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"25","issue":"1","first_page":"114","last_page":"117"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.4426000118255615,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.4426000118255615,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.09049999713897705,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.07419999688863754,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.39890000224113464},{"id":"https://openalex.org/keywords/tracing","display_name":"Tracing","score":0.3709000051021576},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.3260999917984009},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.30239999294281006},{"id":"https://openalex.org/keywords/conventional-memory","display_name":"Conventional memory","score":0.2770000100135803},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.27410000562667847}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7767999768257141},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4731999933719635},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4569000005722046},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.39890000224113464},{"id":"https://openalex.org/C138673069","wikidata":"https://www.wikidata.org/wiki/Q322229","display_name":"Tracing","level":2,"score":0.3709000051021576},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.3260999917984009},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.30239999294281006},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.2994999885559082},{"id":"https://openalex.org/C53838383","wikidata":"https://www.wikidata.org/wiki/Q541148","display_name":"Conventional memory","level":5,"score":0.2770000100135803},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.27410000562667847},{"id":"https://openalex.org/C121684516","wikidata":"https://www.wikidata.org/wiki/Q7600677","display_name":"Computer graphics (images)","level":1,"score":0.26420000195503235},{"id":"https://openalex.org/C18131444","wikidata":"https://www.wikidata.org/wiki/Q163585","display_name":"Memory protection","level":5,"score":0.2599000036716461},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2597000002861023},{"id":"https://openalex.org/C2776321774","wikidata":"https://www.wikidata.org/wiki/Q891131","display_name":"Read-write memory","level":3,"score":0.25619998574256897},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.250900000333786}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/lca.2026.3673181","is_oa":true,"landing_page_url":"https://doi.org/10.1109/lca.2026.3673181","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Architecture Letters","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1109/lca.2026.3673181","is_oa":true,"landing_page_url":"https://doi.org/10.1109/lca.2026.3673181","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Architecture Letters","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"Accurate,":[0],"full-system":[1,137],"physical":[2],"memory":[3,52,58,103,128,154],"traces":[4,59,118,133],"are":[5,31,65],"critical":[6],"for":[7,108,149],"computer":[8],"architecture":[9],"research,":[10],"but":[11],"existing":[12],"collection":[13,75],"methods":[14],"based":[15],"on":[16],"software":[17],"instrumentation":[18,107],"or":[19,34],"simulation":[20],"suffer":[21],"from":[22,60],"a":[23,39,45,49,61,68,73,120,136],"lack":[24],"of":[25,95],"fidelity,":[26],"while":[27],"prior":[28],"hardware-based":[29],"solutions":[30],"often":[32],"intrusive":[33],"proprietary.":[35],"We":[36],"introduce":[37],"CXL-Tracer,":[38],"non-intrusive":[40],"tracing":[41],"framework":[42],"that":[43,89,114],"uses":[44],"commodity":[46],"FPGA":[47],"as":[48,140],"CXL":[50],"Type-3":[51],"device":[53],"to":[54,72,100,132],"capture":[55],"complete,":[56],"high-fidelity":[57],"real":[62],"system.":[63],"Traces":[64],"offloaded":[66],"over":[67],"dedicated":[69],"PCIe":[70],"link":[71],"separate":[74],"server,":[76],"ensuring":[77],"no":[78],"performance":[79],"interference":[80],"with":[81],"the":[82,92],"system":[83,96],"under":[84],"test.":[85],"Our":[86],"evaluation":[87],"demonstrates":[88],"CXL-Tracer":[90,142],"captures":[91],"full":[93],"spectrum":[94],"activity,":[97],"recording":[98],"up":[99],"70x":[101],"more":[102,126],"traffic":[104],"than":[105],"binary":[106],"I/O-heavy":[109],"workloads.":[110],"Furthermore,":[111],"we":[112],"show":[113],"replaying":[115],"these":[116],"real-system":[117],"in":[119],"cycle-accurate":[121],"DRAM":[122],"simulator":[123,138],"yields":[124],"significantly":[125],"realistic":[127],"latency":[129],"results":[130],"compared":[131],"generated":[134],"by":[135],"such":[139],"gem5.":[141],"provides":[143],"an":[144],"accessible":[145],"and":[146,151],"accurate":[147],"platform":[148],"designing":[150],"evaluating":[152],"future":[153],"subsystems.":[155]},"counts_by_year":[],"updated_date":"2026-03-28T06:11:35.319607","created_date":"2026-03-13T00:00:00"}
