{"id":"https://openalex.org/W4414270825","doi":"https://doi.org/10.1109/lca.2025.3611326","title":"Improving Performance on Tiered Memory With Semantic Data Placement","display_name":"Improving Performance on Tiered Memory With Semantic Data Placement","publication_year":2025,"publication_date":"2025-07-01","ids":{"openalex":"https://openalex.org/W4414270825","doi":"https://doi.org/10.1109/lca.2025.3611326"},"language":"en","primary_location":{"id":"doi:10.1109/lca.2025.3611326","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lca.2025.3611326","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Architecture Letters","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5119647197","display_name":"Allen Aboytes","orcid":null},"institutions":[{"id":"https://openalex.org/I185103710","display_name":"University of California, Santa Cruz","ror":"https://ror.org/03s65by71","country_code":"US","type":"education","lineage":["https://openalex.org/I185103710"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Allen Aboytes","raw_affiliation_strings":["University of California, Santa Cruz, CA, USA"],"affiliations":[{"raw_affiliation_string":"University of California, Santa Cruz, CA, USA","institution_ids":["https://openalex.org/I185103710"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5023406554","display_name":"Pankaj Mehra","orcid":"https://orcid.org/0009-0003-3188-243X"},"institutions":[{"id":"https://openalex.org/I52357470","display_name":"The Ohio State University","ror":"https://ror.org/00rs6vg23","country_code":"US","type":"education","lineage":["https://openalex.org/I52357470"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Pankaj Mehra","raw_affiliation_strings":["The Ohio State University, Columbus, OH, USA"],"affiliations":[{"raw_affiliation_string":"The Ohio State University, Columbus, OH, USA","institution_ids":["https://openalex.org/I52357470"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5119647197"],"corresponding_institution_ids":["https://openalex.org/I185103710"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.27326795,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"24","issue":"2","first_page":"297","last_page":"300"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9577000141143799,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9577000141143799,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9473999738693237,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10028","display_name":"Topic Modeling","score":0.9386000037193298,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/allocator","display_name":"Allocator","score":0.8166999816894531},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.7519000172615051},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.6820999979972839},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.6317999958992004},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.589900016784668},{"id":"https://openalex.org/keywords/memory-protection","display_name":"Memory protection","score":0.512499988079071},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.5070000290870667},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.4465000033378601},{"id":"https://openalex.org/keywords/physical-address","display_name":"Physical address","score":0.41999998688697815},{"id":"https://openalex.org/keywords/memory-address","display_name":"Memory address","score":0.4185999929904938}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8831999897956848},{"id":"https://openalex.org/C162262903","wikidata":"https://www.wikidata.org/wiki/Q343527","display_name":"Allocator","level":2,"score":0.8166999816894531},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.7519000172615051},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.6820999979972839},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.6317999958992004},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.589900016784668},{"id":"https://openalex.org/C18131444","wikidata":"https://www.wikidata.org/wiki/Q163585","display_name":"Memory protection","level":5,"score":0.512499988079071},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.5070000290870667},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.4465000033378601},{"id":"https://openalex.org/C41036726","wikidata":"https://www.wikidata.org/wiki/Q844824","display_name":"Physical address","level":3,"score":0.41999998688697815},{"id":"https://openalex.org/C153247305","wikidata":"https://www.wikidata.org/wiki/Q835713","display_name":"Memory address","level":3,"score":0.4185999929904938},{"id":"https://openalex.org/C171675096","wikidata":"https://www.wikidata.org/wiki/Q1143380","display_name":"Extended memory","level":4,"score":0.41350001096725464},{"id":"https://openalex.org/C144240696","wikidata":"https://www.wikidata.org/wiki/Q367204","display_name":"Address space","level":2,"score":0.39640000462532043},{"id":"https://openalex.org/C184337299","wikidata":"https://www.wikidata.org/wiki/Q1437428","display_name":"Semantics (computer science)","level":2,"score":0.38339999318122864},{"id":"https://openalex.org/C39528615","wikidata":"https://www.wikidata.org/wiki/Q1229610","display_name":"Distributed shared memory","level":5,"score":0.37720000743865967},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.3718999922275543},{"id":"https://openalex.org/C28180684","wikidata":"https://www.wikidata.org/wiki/Q4080983","display_name":"Memory safety","level":3,"score":0.36880001425743103},{"id":"https://openalex.org/C2779808786","wikidata":"https://www.wikidata.org/wiki/Q6664603","display_name":"Locality","level":2,"score":0.3528999984264374},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.3440999984741211},{"id":"https://openalex.org/C91481028","wikidata":"https://www.wikidata.org/wiki/Q1054686","display_name":"Distributed memory","level":3,"score":0.3393000066280365},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3253999948501587},{"id":"https://openalex.org/C133371097","wikidata":"https://www.wikidata.org/wiki/Q868014","display_name":"Non-uniform memory access","level":5,"score":0.3199999928474426},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.288100004196167},{"id":"https://openalex.org/C188873839","wikidata":"https://www.wikidata.org/wiki/Q5255045","display_name":"Demand paging","level":5,"score":0.2825999855995178},{"id":"https://openalex.org/C197914299","wikidata":"https://www.wikidata.org/wiki/Q18650","display_name":"Semantic memory","level":3,"score":0.2791999876499176},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.2775000035762787},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.274399995803833},{"id":"https://openalex.org/C82687282","wikidata":"https://www.wikidata.org/wiki/Q66221","display_name":"Auxiliary memory","level":2,"score":0.26179999113082886},{"id":"https://openalex.org/C2781357197","wikidata":"https://www.wikidata.org/wiki/Q5757597","display_name":"High memory","level":2,"score":0.2603999972343445},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.2596000134944916},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.2572999894618988},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.25110000371932983}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/lca.2025.3611326","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lca.2025.3611326","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Architecture Letters","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1974272726","https://openalex.org/W1985229168","https://openalex.org/W2340522713","https://openalex.org/W2933229475","https://openalex.org/W4327930415","https://openalex.org/W4327930439","https://openalex.org/W4387321556","https://openalex.org/W4388041042","https://openalex.org/W4408870850"],"related_works":[],"abstract_inverted_index":{"Memory-intensive":[0],"application":[1,100,120],"working":[2],"sets":[3],"continue":[4],"to":[5,43,48,81,96,102],"grow":[6],"and":[7,60,134,139],"demand":[8],"more":[9,87],"memory.":[10,141],"Far":[11],"memory":[12,20,28,34,40,46,53,58,77,121,127,132,161,168],"technologies":[13],"such":[14],"as":[15],"CXL":[16],"potentially":[17],"solve":[18],"the":[19,45,65,104,117],"capacity":[21],"bottleneck.":[22],"However,":[23],"efficient":[24],"use":[25],"of":[26,106,119,165],"far":[27,140],"requires":[29],"careful":[30],"data":[31,83,88,98,147],"placement":[32,148],"among":[33],"tiers.":[35],"Recent":[36],"work":[37],"uses":[38,158],"page-based":[39],"tiering":[41,54,169],"systems":[42,55],"expand":[44],"available":[47],"applications.":[49],"Unfortunately,":[50],"most":[51],"state-of-the-art":[52,167],"largely":[56],"ignore":[57],"allocation":[59,78],"prioritize":[61],"placing":[62],"pages":[63,136],"in":[64,86],"fast":[66],"tier":[67],"while":[68],"space":[69],"remains":[70],"available.":[71],"Relying":[72],"on":[73,163],"transparent":[74],"methods":[75],"for":[76],"can":[79],"lead":[80],"suboptimal":[82],"placement,":[84],"resulting":[85],"migration.":[89],"To":[90],"address":[91],"these":[92],"issues,":[93],"we":[94],"propose":[95],"place":[97],"using":[99],"semantics":[101],"increase":[103],"locality":[105],"reference":[107],"within":[108],"pages.":[109],"We":[110],"present":[111],"M2T,":[112],"a":[113,130,154,159],"system":[114],"that":[115,145,157],"optimizes":[116],"layout":[118],"allocations":[122],"by":[123],"grouping":[124],"semantically":[125],"related":[126],"objects":[128],"with":[129],"custom":[131],"allocator":[133,162],"migrates":[135],"between":[137],"local":[138],"Our":[142],"evaluation":[143],"demonstrates":[144],"semantic":[146],"achieves":[149],"3.39\u20134.69\u00d7":[150],"higher":[151],"throughput":[152],"than":[153],"key-value":[155],"store":[156],"standard":[160],"top":[164],"various":[166],"systems.":[170]},"counts_by_year":[],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}