{"id":"https://openalex.org/W4413344046","doi":"https://doi.org/10.1109/lca.2025.3600588","title":"PIMsynth: A Unified Compiler Framework for Bit-Serial Processing-in-Memory Architectures","display_name":"PIMsynth: A Unified Compiler Framework for Bit-Serial Processing-in-Memory Architectures","publication_year":2025,"publication_date":"2025-07-01","ids":{"openalex":"https://openalex.org/W4413344046","doi":"https://doi.org/10.1109/lca.2025.3600588"},"language":"en","primary_location":{"id":"doi:10.1109/lca.2025.3600588","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lca.2025.3600588","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Architecture Letters","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030409044","display_name":"Deyuan Guo","orcid":null},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Deyuan Guo","raw_affiliation_strings":["University of Virginia, Charlottesville, VA, USA"],"raw_orcid":"https://orcid.org/0009-0004-1756-1784","affiliations":[{"raw_affiliation_string":"University of Virginia, Charlottesville, VA, USA","institution_ids":["https://openalex.org/I51556381"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108831439","display_name":"Mohammadhosein Gholamrezaei","orcid":null},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mohammadhosein Gholamrezaei","raw_affiliation_strings":["University of Virginia, Charlottesville, VA, USA"],"raw_orcid":"https://orcid.org/0000-0001-5549-2901","affiliations":[{"raw_affiliation_string":"University of Virginia, Charlottesville, VA, USA","institution_ids":["https://openalex.org/I51556381"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033193520","display_name":"Matthew Hofmann","orcid":"https://orcid.org/0000-0003-4204-6675"},"institutions":[{"id":"https://openalex.org/I205783295","display_name":"Cornell University","ror":"https://ror.org/05bnh6r87","country_code":"US","type":"education","lineage":["https://openalex.org/I205783295"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Matthew Hofmann","raw_affiliation_strings":["Cornell University, Ithaca, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cornell University, Ithaca, NY, USA","institution_ids":["https://openalex.org/I205783295"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010095801","display_name":"Ashish Venkat","orcid":"https://orcid.org/0000-0003-1959-8463"},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ashish Venkat","raw_affiliation_strings":["University of Virginia, Charlottesville, VA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Virginia, Charlottesville, VA, USA","institution_ids":["https://openalex.org/I51556381"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037210004","display_name":"Zhiru Zhang","orcid":"https://orcid.org/0000-0002-0778-0308"},"institutions":[{"id":"https://openalex.org/I205783295","display_name":"Cornell University","ror":"https://ror.org/05bnh6r87","country_code":"US","type":"education","lineage":["https://openalex.org/I205783295"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zhiru Zhang","raw_affiliation_strings":["Cornell University, Ithaca, NY, USA"],"raw_orcid":"https://orcid.org/0000-0002-0778-0308","affiliations":[{"raw_affiliation_string":"Cornell University, Ithaca, NY, USA","institution_ids":["https://openalex.org/I205783295"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074818897","display_name":"Kevin Skadron","orcid":"https://orcid.org/0000-0002-8091-9302"},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kevin Skadron","raw_affiliation_strings":["University of Virginia, Charlottesville, VA, USA"],"raw_orcid":"https://orcid.org/0000-0002-8091-9302","affiliations":[{"raw_affiliation_string":"University of Virginia, Charlottesville, VA, USA","institution_ids":["https://openalex.org/I51556381"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.12835602,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"24","issue":"2","first_page":"277","last_page":"280"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9926999807357788,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9926999807357788,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9921000003814697,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9714000225067139,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8702971339225769},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.6318982839584351},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5474130511283875},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5373543500900269},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.5082911849021912},{"id":"https://openalex.org/keywords/bit","display_name":"Bit (key)","score":0.4404405951499939},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3207070231437683},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.09651705622673035}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8702971339225769},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.6318982839584351},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5474130511283875},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5373543500900269},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.5082911849021912},{"id":"https://openalex.org/C117011727","wikidata":"https://www.wikidata.org/wiki/Q1278488","display_name":"Bit (key)","level":2,"score":0.4404405951499939},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3207070231437683},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.09651705622673035}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/lca.2025.3600588","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lca.2025.3600588","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Architecture Letters","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1528837436","https://openalex.org/W2749371864","https://openalex.org/W2979874885","https://openalex.org/W3016765354","https://openalex.org/W3022378354","https://openalex.org/W3155004489","https://openalex.org/W4246166885","https://openalex.org/W4285676464","https://openalex.org/W4360831799","https://openalex.org/W4393407315","https://openalex.org/W4393407317","https://openalex.org/W4401568236","https://openalex.org/W4406266076","https://openalex.org/W4409248632"],"related_works":["https://openalex.org/W4327546585","https://openalex.org/W4240253816","https://openalex.org/W3096456556","https://openalex.org/W2411923897","https://openalex.org/W2169584677","https://openalex.org/W1713081424","https://openalex.org/W2127315869","https://openalex.org/W1523769955","https://openalex.org/W2245390655","https://openalex.org/W4379536100"],"abstract_inverted_index":{"Bit-serial":[0],"processing-in-memory":[1],"(PIM)":[2],"architectures":[3],"have":[4],"been":[5],"extensively":[6],"studied,":[7],"yet":[8],"a":[9,24,70,78],"standardized":[10],"tool":[11],"for":[12,30,51,84],"generating":[13],"efficient":[14,85],"bit-serial":[15,31,53,79,86,114],"code":[16,50,67,87,115,124],"is":[17,125],"lacking,":[18],"hindering":[19],"fair":[20],"comparisons.":[21],"We":[22],"present":[23],"fully":[25],"automated":[26],"compiler":[27,41,111],"framework,":[28],"PIMsynth,":[29],"PIM":[32,54,99,121],"architectures,":[33],"targeting":[34],"both":[35],"digital":[36,118],"and":[37,46,65,92,119],"analog":[38,120],"substrates.":[39],"The":[40],"takes":[42],"Verilog":[43],"as":[44],"input":[45],"generates":[47,112],"optimized":[48],"micro-operation":[49],"programmable":[52],"backends.":[55],"Our":[56,123],"flow":[57],"integrates":[58],"logic":[59],"synthesis,":[60],"optimization":[61],"steps,":[62],"instruction":[63],"scheduling,":[64],"backend":[66],"generation":[68],"into":[69],"unified":[71],"toolchain.":[72],"With":[73],"the":[74,110],"compiler,":[75],"we":[76,95],"provide":[77],"compilation":[80],"benchmark":[81],"suite":[82],"designed":[83],"generation.":[88],"To":[89],"enable":[90],"correctness":[91],"performance":[93],"validation,":[94],"extend":[96],"an":[97],"existing":[98],"simulator":[100],"to":[101],"support":[102],"compiler-generated":[103],"micro-op-level":[104],"workloads.":[105],"Preliminary":[106],"results":[107],"demonstrate":[108],"that":[109],"competitive":[113],"within$1.08\\times$and$1.54\\times$of":[116],"hand-optimized":[117],"baselines.":[122],"publicly":[126],"available":[127],"athttps://github.com/UVA-LavaLab/PIMsynth.":[128]},"counts_by_year":[],"updated_date":"2026-07-29T09:40:50.615796","created_date":"2025-10-10T00:00:00"}
