{"id":"https://openalex.org/W4411948931","doi":"https://doi.org/10.1109/lca.2025.3585312","title":"PUDTune: Multi-Level Charging for High-Precision Calibration in Processing-Using-DRAM","display_name":"PUDTune: Multi-Level Charging for High-Precision Calibration in Processing-Using-DRAM","publication_year":2025,"publication_date":"2025-07-01","ids":{"openalex":"https://openalex.org/W4411948931","doi":"https://doi.org/10.1109/lca.2025.3585312"},"language":"en","primary_location":{"id":"doi:10.1109/lca.2025.3585312","is_oa":true,"landing_page_url":"https://doi.org/10.1109/lca.2025.3585312","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Architecture Letters","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://doi.org/10.1109/lca.2025.3585312","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5047295118","display_name":"Tatsuya Kubo","orcid":"https://orcid.org/0009-0005-1523-3063"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Tatsuya Kubo","raw_affiliation_strings":["University of Tokyo, Tokyo, Japan","University of Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5114958735","display_name":"Daichi Tokuda","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Daichi Tokuda","raw_affiliation_strings":["University of Tokyo, Tokyo, Japan","University of Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111655014","display_name":"Lei Qu","orcid":null},"institutions":[{"id":"https://openalex.org/I4210113369","display_name":"Microsoft Research Asia (China)","ror":"https://ror.org/0300m5276","country_code":"CN","type":"company","lineage":["https://openalex.org/I1290206253","https://openalex.org/I4210113369"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Lei Qu","raw_affiliation_strings":["Microsoft Research, Beijing, China","Microsoft Research, Japan"],"affiliations":[{"raw_affiliation_string":"Microsoft Research, Beijing, China","institution_ids":["https://openalex.org/I4210113369"]},{"raw_affiliation_string":"Microsoft Research, Japan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019935150","display_name":"Ting Cao","orcid":"https://orcid.org/0000-0002-0596-578X"},"institutions":[{"id":"https://openalex.org/I4210113369","display_name":"Microsoft Research Asia (China)","ror":"https://ror.org/0300m5276","country_code":"CN","type":"company","lineage":["https://openalex.org/I1290206253","https://openalex.org/I4210113369"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ting Cao","raw_affiliation_strings":["Microsoft Research, Beijing, China","Microsoft Research, Japan"],"affiliations":[{"raw_affiliation_string":"Microsoft Research, Beijing, China","institution_ids":["https://openalex.org/I4210113369"]},{"raw_affiliation_string":"Microsoft Research, Japan","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059694753","display_name":"Shinya Takamaeda-Yamazaki","orcid":"https://orcid.org/0000-0003-3441-1695"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Shinya Takamaeda-Yamazaki","raw_affiliation_strings":["University of Tokyo, Tokyo, Japan","University of Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5047295118"],"corresponding_institution_ids":["https://openalex.org/I74801974"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.16068447,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"24","issue":"2","first_page":"245","last_page":"248"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9959999918937683,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9959999918937683,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9957000017166138,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.994700014591217,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.8531290292739868},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7523494362831116},{"id":"https://openalex.org/keywords/calibration","display_name":"Calibration","score":0.7161009311676025},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.43016839027404785},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.36199378967285156},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.32428911328315735}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.8531290292739868},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7523494362831116},{"id":"https://openalex.org/C165838908","wikidata":"https://www.wikidata.org/wiki/Q736777","display_name":"Calibration","level":2,"score":0.7161009311676025},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.43016839027404785},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.36199378967285156},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.32428911328315735},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/lca.2025.3585312","is_oa":true,"landing_page_url":"https://doi.org/10.1109/lca.2025.3585312","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Architecture Letters","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1109/lca.2025.3585312","is_oa":true,"landing_page_url":"https://doi.org/10.1109/lca.2025.3585312","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Architecture Letters","raw_type":"journal-article"},"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.6399999856948853}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W2979874885","https://openalex.org/W3187200870","https://openalex.org/W4226402784","https://openalex.org/W4308083578","https://openalex.org/W4379033852","https://openalex.org/W4406457670","https://openalex.org/W6910665659"],"related_works":["https://openalex.org/W3120961607","https://openalex.org/W4401568740","https://openalex.org/W3148568549","https://openalex.org/W2098207691","https://openalex.org/W1648516568","https://openalex.org/W361036515","https://openalex.org/W2161286015","https://openalex.org/W2269474412","https://openalex.org/W2433923775","https://openalex.org/W80860381"],"abstract_inverted_index":{"Recently,":[0],"practical":[1,35],"analog":[2],"in-memory":[3],"computing":[4],"has":[5],"been":[6],"realized":[7],"using":[8,39],"unmodified":[9],"commercial":[10],"DRAM":[11,24,89,107],"modules.":[12],"The":[13],"underlying":[14],"Processing-Using-DRAM":[15],"(PUD)":[16],"techniques":[17],"enable":[18],"high-throughput":[19],"bitwise":[20],"operations":[21],"directly":[22],"within":[23],"arrays.":[25],"However,":[26],"the":[27,64,99,112],"presence":[28],"of":[29,66,88,114],"inherent":[30],"error-prone":[31],"columns":[32,42,68,116],"hinders":[33],"PUD's":[34,50],"adoption.":[36],"While":[37],"selectively":[38],"only":[40],"error-free":[41,67,115],"would":[43],"ensure":[44],"reliability,":[45],"this":[46],"approach":[47],"significantly":[48],"reduces":[49],"computational":[51],"throughput.":[52],"This":[53],"paper":[54],"presents":[55],"PUDTune,":[56],"a":[57],"novel":[58],"high-precision":[59],"calibration":[60],"technique":[61],"for":[62,73],"increasing":[63],"number":[65,113],"in":[69],"PUD.":[70],"PUDTune":[71,91,110],"compensates":[72],"errors":[74],"by":[75,117,128],"applying":[76],"pre-identified":[77],"column-specific":[78],"offsets":[79],"to":[80,120],"PUD":[81],"operations.":[82],"By":[83],"leveraging":[84],"multi-level":[85],"charge":[86],"states":[87],"cells,":[90],"generates":[92],"fine-grained":[93],"and":[94,125,130],"wide-range":[95],"offset":[96],"variations":[97],"despite":[98],"limited":[100],"available":[101],"rows.":[102],"Our":[103],"experiments":[104],"with":[105],"DDR4":[106],"demonstrate":[108],"that":[109],"increases":[111],"1.81\u00d7":[118],"compared":[119],"conventional":[121],"implementations,":[122],"improving":[123],"addition":[124],"multiplication":[126],"throughput":[127],"1.88\u00d7":[129],"1.89\u00d7":[131],"respectively.":[132]},"counts_by_year":[],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}