{"id":"https://openalex.org/W4409796338","doi":"https://doi.org/10.1109/lca.2025.3564535","title":"Cache and Near-Data Co-Design for Chiplets","display_name":"Cache and Near-Data Co-Design for Chiplets","publication_year":2025,"publication_date":"2025-01-01","ids":{"openalex":"https://openalex.org/W4409796338","doi":"https://doi.org/10.1109/lca.2025.3564535"},"language":"en","primary_location":{"id":"doi:10.1109/lca.2025.3564535","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lca.2025.3564535","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Architecture Letters","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5117309102","display_name":"Arteen Abrishami","orcid":null},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Arteen Abrishami","raw_affiliation_strings":["University of California, Los Angeles, CA, USA"],"affiliations":[{"raw_affiliation_string":"University of California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I161318765"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101964447","display_name":"Zhengrong Wang","orcid":"https://orcid.org/0000-0001-7439-440X"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zhengrong Wang","raw_affiliation_strings":["University of California, Los Angeles, CA, USA"],"affiliations":[{"raw_affiliation_string":"University of California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I161318765"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5006723758","display_name":"Tony Nowatzki","orcid":"https://orcid.org/0000-0001-8483-3824"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tony Nowatzki","raw_affiliation_strings":["University of California, Los Angeles, CA, USA"],"affiliations":[{"raw_affiliation_string":"University of California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I161318765"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5117309102"],"corresponding_institution_ids":["https://openalex.org/I161318765"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.08919123,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"24","issue":"1","first_page":"149","last_page":"152"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9941999912261963,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7864375710487366},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.555612325668335},{"id":"https://openalex.org/keywords/smart-cache","display_name":"Smart Cache","score":0.42850032448768616},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.41959431767463684},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.3752303719520569},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3459346890449524},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.32758721709251404},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.2919849157333374}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7864375710487366},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.555612325668335},{"id":"https://openalex.org/C167713795","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"Smart Cache","level":5,"score":0.42850032448768616},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.41959431767463684},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.3752303719520569},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3459346890449524},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.32758721709251404},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.2919849157333374}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/lca.2025.3564535","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lca.2025.3564535","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Architecture Letters","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W109781734","https://openalex.org/W2080592089","https://openalex.org/W2086112773","https://openalex.org/W3011446983","https://openalex.org/W3211664117","https://openalex.org/W4220980777","https://openalex.org/W4280590405","https://openalex.org/W4308083596","https://openalex.org/W4313192083","https://openalex.org/W4379115896","https://openalex.org/W4392719523","https://openalex.org/W6859450238"],"related_works":["https://openalex.org/W2031173804","https://openalex.org/W2114386333","https://openalex.org/W2509523906","https://openalex.org/W2363769136","https://openalex.org/W2148571123","https://openalex.org/W3085471909","https://openalex.org/W2041820064","https://openalex.org/W198173854","https://openalex.org/W2404820046","https://openalex.org/W2324141783"],"abstract_inverted_index":{"Vendors":[0],"are":[1],"increasingly":[2],"adopting":[3],"chiplet-based":[4],"designs":[5,36,76],"to":[6,40,53,62,93,96],"manage":[7],"cost":[8],"for":[9,103],"large-scale":[10,84],"multi-cores.":[11],"While":[12],"near-data":[13,104,118],"computing,":[14],"a":[15,56,78,110],"paradigm":[16,51],"involving":[17],"offloading":[18],"computation":[19,59],"near":[20],"where":[21,58],"data":[22],"is":[23,60],"located":[24],"in":[25,30,55,91,134],"memory,":[26],"has":[27],"been":[28],"studied":[29],"the":[31,50,66,98],"context":[32],"of":[33,80],"monolithic":[34],"chip":[35],"\u2013":[37],"its":[38],"applications":[39],"chiplets":[41,54],"remain":[42],"unexplored.":[43],"In":[44],"this":[45],"letter,":[46],"we":[47],"explore":[48,70],"how":[49,95],"extends":[52],"system":[57],"offloaded":[61],"accelerators":[63],"collocated":[64],"within":[65],"last-level-cache":[67,75,116],"structure.":[68],"We":[69,106],"both":[71,83],"shared":[72,115],"and":[73,87,100],"private":[74],"across":[77],"variety":[79],"different":[81],"workloads,":[82,90,127],"graph":[85,126],"computations":[86],"more":[88],"regular-access":[89],"order":[92],"understand":[94],"optimize":[97],"cache":[99],"topology":[101],"design":[102],"workloads.":[105],"find":[107],"that":[108],"with":[109,114],"mesh":[111],"chiplet":[112],"architecture":[113],"(LLC),":[117],"optimization":[119],"can":[120],"achieve":[121],"an":[122,129],"8.70\u00d7":[123],"speedup":[124],"on":[125],"providing":[128],"even":[130],"greater":[131],"benefit":[132],"than":[133],"traditional":[135],"systems.":[136]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
