{"id":"https://openalex.org/W4409261997","doi":"https://doi.org/10.1109/lca.2025.3558808","title":"Analyzing and Exploiting Memory Hierarchy Parallelism With MLP Stacks","display_name":"Analyzing and Exploiting Memory Hierarchy Parallelism With MLP Stacks","publication_year":2025,"publication_date":"2025-01-01","ids":{"openalex":"https://openalex.org/W4409261997","doi":"https://doi.org/10.1109/lca.2025.3558808"},"language":"en","primary_location":{"id":"doi:10.1109/lca.2025.3558808","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lca.2025.3558808","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Architecture Letters","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5114518756","display_name":"Adnan Hasnat","orcid":null},"institutions":[{"id":"https://openalex.org/I118347636","display_name":"Australian National University","ror":"https://ror.org/019wvm592","country_code":"AU","type":"education","lineage":["https://openalex.org/I118347636"]}],"countries":["AU"],"is_corresponding":true,"raw_author_name":"Adnan Hasnat","raw_affiliation_strings":["School of Computing, Australian National University, Canberra, ACT, Australia","School of Computing, Australian National University, Australia"],"affiliations":[{"raw_affiliation_string":"School of Computing, Australian National University, Canberra, ACT, Australia","institution_ids":["https://openalex.org/I118347636"]},{"raw_affiliation_string":"School of Computing, Australian National University, Australia","institution_ids":["https://openalex.org/I118347636"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006011049","display_name":"Wim Heirman","orcid":"https://orcid.org/0000-0003-2286-1525"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Wim Heirman","raw_affiliation_strings":["Intel Belgium, Kontich, Belgium","Intel Belgium"],"affiliations":[{"raw_affiliation_string":"Intel Belgium, Kontich, Belgium","institution_ids":[]},{"raw_affiliation_string":"Intel Belgium","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5019108357","display_name":"Shoaib Akram","orcid":"https://orcid.org/0000-0003-2388-0517"},"institutions":[{"id":"https://openalex.org/I118347636","display_name":"Australian National University","ror":"https://ror.org/019wvm592","country_code":"AU","type":"education","lineage":["https://openalex.org/I118347636"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"Shoaib Akram","raw_affiliation_strings":["School of Computing, Australian National University, Canberra, ACT, Australia","School of Computing, Australian National University, Australia"],"affiliations":[{"raw_affiliation_string":"School of Computing, Australian National University, Canberra, ACT, Australia","institution_ids":["https://openalex.org/I118347636"]},{"raw_affiliation_string":"School of Computing, Australian National University, Australia","institution_ids":["https://openalex.org/I118347636"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5114518756"],"corresponding_institution_ids":["https://openalex.org/I118347636"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.07392068,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"24","issue":"1","first_page":"125","last_page":"128"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9265999794006348,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9265999794006348,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9047999978065491,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.856699526309967},{"id":"https://openalex.org/keywords/parallelism","display_name":"Parallelism (grammar)","score":0.6654222011566162},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.6648368239402771},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6172831058502197},{"id":"https://openalex.org/keywords/hierarchy","display_name":"Hierarchy","score":0.5390052795410156},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5056033134460449},{"id":"https://openalex.org/keywords/task-parallelism","display_name":"Task parallelism","score":0.46254584193229675},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.3608965277671814},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.10506805777549744}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.856699526309967},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.6654222011566162},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.6648368239402771},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6172831058502197},{"id":"https://openalex.org/C31170391","wikidata":"https://www.wikidata.org/wiki/Q188619","display_name":"Hierarchy","level":2,"score":0.5390052795410156},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5056033134460449},{"id":"https://openalex.org/C42992933","wikidata":"https://www.wikidata.org/wiki/Q691169","display_name":"Task parallelism","level":3,"score":0.46254584193229675},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3608965277671814},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.10506805777549744},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C34447519","wikidata":"https://www.wikidata.org/wiki/Q179522","display_name":"Market economy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/lca.2025.3558808","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lca.2025.3558808","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Architecture Letters","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1490845105","https://openalex.org/W2127643746","https://openalex.org/W2154001575","https://openalex.org/W2953698097","https://openalex.org/W4244721345","https://openalex.org/W4283651665"],"related_works":["https://openalex.org/W2950520577","https://openalex.org/W1501159154","https://openalex.org/W74409296","https://openalex.org/W2003935582","https://openalex.org/W2567390125","https://openalex.org/W4405088460","https://openalex.org/W1554644772","https://openalex.org/W305742777","https://openalex.org/W2940653809","https://openalex.org/W2468095077"],"abstract_inverted_index":{"Obtaining":[0],"high":[1,10],"instruction":[2,133],"throughput":[3],"on":[4],"modern":[5],"CPUs":[6],"requires":[7,36],"generating":[8],"a":[9,21,45,74,111],"degree":[11],"of":[12,48,90],"memory-level":[13],"parallelism":[14,35,99],"(MLP).":[15],"MLP":[16,49,52,72,108],"is":[17,70],"typically":[18],"reported":[19],"as":[20],"quantitative":[22],"metric":[23],"at":[24],"the":[25,30,87,107,120],"DRAM":[26],"level.":[27,93],"However,":[28],"understanding":[29],"reasons":[31],"that":[32,76,118],"hinder":[33],"memory":[34,92],"more":[37],"insightful":[38],"metrics":[39],"and":[40,55,58,62,80,102,114,129],"visualizations.":[41],"This":[42],"paper":[43],"proposes":[44],"new":[46],"taxonomy":[47],"metrics,":[50,79],"splitting":[51],"into":[53],"core":[54],"prefetch":[56],"components":[57],"measuring":[59],"both":[60],"miss":[61],"hit":[63],"cache":[64],"level":[65],"parallelism.":[66],"Our":[67],"key":[68],"contribution":[69,89],"an":[71],"stack,":[73],"visualization":[75],"integrates":[77],"these":[78],"connects":[81],"then":[82],"to":[83],"performance":[84],"by":[85],"showing":[86],"CPI":[88],"each":[91],"The":[94],"stack":[95,109],"also":[96],"shows":[97],"speculative":[98],"from":[100],"dependency-bound":[101],"structural-hazard-bound":[103],"loads.":[104],"We":[105],"implement":[106],"in":[110],"processor":[112],"simulator":[113],"conduct":[115],"case":[116],"studies":[117],"demonstrate":[119],"potential":[121],"for":[122],"targeting":[123],"software":[124,127],"optimizations":[125],"(e.g.,":[126,132],"prefetching),":[128],"hardware":[130],"improvements":[131],"window":[134],"sizing).":[135]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}