{"id":"https://openalex.org/W4407949399","doi":"https://doi.org/10.1109/lca.2025.3545799","title":"A Data Prefetcher-Based 1000-Core RISC-V Processor for Efficient Processing of Graph Neural Networks","display_name":"A Data Prefetcher-Based 1000-Core RISC-V Processor for Efficient Processing of Graph Neural Networks","publication_year":2025,"publication_date":"2025-01-01","ids":{"openalex":"https://openalex.org/W4407949399","doi":"https://doi.org/10.1109/lca.2025.3545799"},"language":"en","primary_location":{"id":"doi:10.1109/lca.2025.3545799","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lca.2025.3545799","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Architecture Letters","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048129220","display_name":"Omer Khan","orcid":"https://orcid.org/0000-0001-6293-7403"},"institutions":[{"id":"https://openalex.org/I140172145","display_name":"University of Connecticut","ror":"https://ror.org/02der9h97","country_code":"US","type":"education","lineage":["https://openalex.org/I140172145"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Omer Khan","raw_affiliation_strings":["Electrical and Computer Engineering, University of Connecticut, Storrs, CT, USA"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, University of Connecticut, Storrs, CT, USA","institution_ids":["https://openalex.org/I140172145"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5048129220"],"corresponding_institution_ids":["https://openalex.org/I140172145"],"apc_list":null,"apc_paid":null,"fwci":1.2181,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.76293152,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":98},"biblio":{"volume":"24","issue":"1","first_page":"73","last_page":"76"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12292","display_name":"Graph Theory and Algorithms","score":0.9664999842643738,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12292","display_name":"Graph Theory and Algorithms","score":0.9664999842643738,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12702","display_name":"Brain Tumor Detection and Classification","score":0.9613999724388123,"subfield":{"id":"https://openalex.org/subfields/2808","display_name":"Neurology"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9537000060081482,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8468536138534546},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.5204746723175049},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5100353360176086},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5067244172096252},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.4740210175514221},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.4433676600456238},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.423002690076828},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.23914176225662231},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.2373039722442627},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.21135291457176208}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8468536138534546},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.5204746723175049},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5100353360176086},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5067244172096252},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.4740210175514221},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.4433676600456238},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.423002690076828},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.23914176225662231},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.2373039722442627},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.21135291457176208}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/lca.2025.3545799","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lca.2025.3545799","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Architecture Letters","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.5799999833106995}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320306087","display_name":"Semiconductor Research Corporation","ror":"https://ror.org/047z4n946"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W2161522487","https://openalex.org/W2416944327","https://openalex.org/W3090369187","https://openalex.org/W3105753905","https://openalex.org/W4206371601","https://openalex.org/W4360831960","https://openalex.org/W4381894545","https://openalex.org/W6760045743","https://openalex.org/W6797677657","https://openalex.org/W7047676081"],"related_works":["https://openalex.org/W1993191611","https://openalex.org/W2023938924","https://openalex.org/W2918840249","https://openalex.org/W1991859582","https://openalex.org/W2110053126","https://openalex.org/W2079303253","https://openalex.org/W2104702637","https://openalex.org/W4248099758","https://openalex.org/W2979015021","https://openalex.org/W2035206467"],"abstract_inverted_index":{"Graphs-based":[0],"neural":[1],"networks":[2],"have":[3],"seen":[4],"tremendous":[5],"adoption":[6],"to":[7,33,55,66,83,92,101,123],"perform":[8],"complex":[9],"predictive":[10],"analytics":[11],"on":[12],"massive":[13,48,85],"real-world":[14],"graphs.":[15],"The":[16],"trend":[17],"in":[18,53,87,99],"hardware":[19,45,100],"acceleration":[20],"has":[21],"identified":[22],"significant":[23],"challenges":[24],"with":[25,112],"harnessing":[26],"graph":[27],"locality":[28],"and":[29,35,50],"workload":[30],"imbalance":[31],"due":[32],"ultra-sparse":[34],"irregular":[36],"matrix":[37,90],"computations":[38],"at":[39,59,118],"a":[40,94,109,113],"massively":[41],"parallel":[42,57],"scale.":[43],"State-of-the-art":[44],"accelerators":[46],"utilize":[47],"multithreading":[49],"asynchronous":[51],"execution":[52],"GPUs":[54],"achieve":[56,93,102],"performance":[58,128],"high":[60],"power":[61],"consumption.":[62],"This":[63],"paper":[64],"aims":[65],"bridge":[67],"the":[68,72,88,119],"power-performance":[69,104],"gap":[70],"using":[71],"energy":[73],"efficiency-centric":[74],"RISC-V":[75,79],"ecosystem.":[76],"A":[77],"1000-core":[78],"processor":[80],"is":[81],"proposed":[82],"unlock":[84],"parallelism":[86],"graphs-based":[89],"operators":[91],"low-latency":[95],"data":[96,116],"access":[97],"paradigm":[98],"robust":[103],"scaling.":[105],"Each":[106],"core":[107],"implements":[108],"single-threaded":[110],"pipeline":[111],"novel":[114],"graph-aware":[115],"prefetcher":[117],"1000":[120],"cores":[121],"scale":[122],"deliver":[124],"an":[125],"average":[126],"20\u00d7":[127],"per":[129],"watt":[130],"advantage":[131],"over":[132],"state-of-the-art":[133],"NVIDIA":[134],"GPU.":[135]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2026-04-09T08:11:56.329763","created_date":"2025-10-10T00:00:00"}
