{"id":"https://openalex.org/W4392940676","doi":"https://doi.org/10.1109/lca.2024.3379002","title":"Approximate Multiplier Design With LFSR-Based Stochastic Sequence Generators for Edge AI","display_name":"Approximate Multiplier Design With LFSR-Based Stochastic Sequence Generators for Edge AI","publication_year":2024,"publication_date":"2024-01-01","ids":{"openalex":"https://openalex.org/W4392940676","doi":"https://doi.org/10.1109/lca.2024.3379002"},"language":"en","primary_location":{"id":"doi:10.1109/lca.2024.3379002","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lca.2024.3379002","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Architecture Letters","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103028924","display_name":"Mrinmay Sasmal","orcid":"https://orcid.org/0009-0009-7064-5510"},"institutions":[{"id":"https://openalex.org/I114845381","display_name":"National Institute of Technology Calicut","ror":"https://ror.org/03yyd7552","country_code":"IN","type":"education","lineage":["https://openalex.org/I114845381"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Mrinmay Sasmal","raw_affiliation_strings":["Department of Electronics and Communication Engineering, National Institute of Technology Calicut, Kozhikode, Kerala, India"],"raw_orcid":"https://orcid.org/0009-0009-7064-5510","affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, National Institute of Technology Calicut, Kozhikode, Kerala, India","institution_ids":["https://openalex.org/I114845381"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019861813","display_name":"Tresa Joseph","orcid":"https://orcid.org/0000-0002-2624-376X"},"institutions":[{"id":"https://openalex.org/I114845381","display_name":"National Institute of Technology Calicut","ror":"https://ror.org/03yyd7552","country_code":"IN","type":"education","lineage":["https://openalex.org/I114845381"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Tresa Joseph","raw_affiliation_strings":["Department of Electronics and Communication Engineering, National Institute of Technology Calicut, Kozhikode, Kerala, India"],"raw_orcid":"https://orcid.org/0000-0002-2624-376X","affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, National Institute of Technology Calicut, Kozhikode, Kerala, India","institution_ids":["https://openalex.org/I114845381"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5071621923","display_name":"T. S. Bindiya","orcid":null},"institutions":[{"id":"https://openalex.org/I114845381","display_name":"National Institute of Technology Calicut","ror":"https://ror.org/03yyd7552","country_code":"IN","type":"education","lineage":["https://openalex.org/I114845381"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Bindiya T. S.","raw_affiliation_strings":["Department of Electronics and Communication Engineering, National Institute of Technology Calicut, Kozhikode, Kerala, India"],"raw_orcid":"https://orcid.org/0000-0002-8406-1833","affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, National Institute of Technology Calicut, Kozhikode, Kerala, India","institution_ids":["https://openalex.org/I114845381"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I114845381"],"apc_list":null,"apc_paid":null,"fwci":3.4492,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.93321748,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"23","issue":"1","first_page":"91","last_page":"94"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9933000206947327,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9930999875068665,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/linear-feedback-shift-register","display_name":"Linear feedback shift register","score":0.7680310010910034},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.6652570366859436},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6650683879852295},{"id":"https://openalex.org/keywords/sequence","display_name":"Sequence (biology)","score":0.6456426382064819},{"id":"https://openalex.org/keywords/enhanced-data-rates-for-gsm-evolution","display_name":"Enhanced Data Rates for GSM Evolution","score":0.5009369850158691},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.4986298084259033},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.44402840733528137},{"id":"https://openalex.org/keywords/shift-register","display_name":"Shift register","score":0.4157121479511261},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.3687661588191986},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3459407687187195},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3444324731826782},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.21646186709403992},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.11567732691764832}],"concepts":[{"id":"https://openalex.org/C159862308","wikidata":"https://www.wikidata.org/wiki/Q681101","display_name":"Linear feedback shift register","level":4,"score":0.7680310010910034},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.6652570366859436},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6650683879852295},{"id":"https://openalex.org/C2778112365","wikidata":"https://www.wikidata.org/wiki/Q3511065","display_name":"Sequence (biology)","level":2,"score":0.6456426382064819},{"id":"https://openalex.org/C162307627","wikidata":"https://www.wikidata.org/wiki/Q204833","display_name":"Enhanced Data Rates for GSM Evolution","level":2,"score":0.5009369850158691},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.4986298084259033},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.44402840733528137},{"id":"https://openalex.org/C49654631","wikidata":"https://www.wikidata.org/wiki/Q746165","display_name":"Shift register","level":3,"score":0.4157121479511261},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.3687661588191986},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3459407687187195},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3444324731826782},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.21646186709403992},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.11567732691764832},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C54355233","wikidata":"https://www.wikidata.org/wiki/Q7162","display_name":"Genetics","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/lca.2024.3379002","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lca.2024.3379002","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Architecture Letters","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W2219959730","https://openalex.org/W2730834423","https://openalex.org/W2742536119","https://openalex.org/W2799283557","https://openalex.org/W2979624870","https://openalex.org/W3001688831","https://openalex.org/W3004421177","https://openalex.org/W3047528894","https://openalex.org/W3184528658","https://openalex.org/W4206588195","https://openalex.org/W4220829081","https://openalex.org/W4323262680","https://openalex.org/W4323967912","https://openalex.org/W4377823167","https://openalex.org/W4379880575","https://openalex.org/W4385043607","https://openalex.org/W6851045396"],"related_works":["https://openalex.org/W1991602179","https://openalex.org/W2623444083","https://openalex.org/W75082849","https://openalex.org/W3157572643","https://openalex.org/W2391979783","https://openalex.org/W2375911758","https://openalex.org/W3093740217","https://openalex.org/W3011195299","https://openalex.org/W1984915767","https://openalex.org/W2101477403"],"abstract_inverted_index":{"This":[0],"paper":[1],"introduces":[2],"an":[3],"innovative":[4],"approximate":[5],"multiplier":[6],"(AM)":[7],"architecture":[8],"that":[9],"leverages":[10],"stochastically":[11],"generated":[12],"bit":[13],"streams":[14],"through":[15],"the":[16,52],"Linear":[17],"Feedback":[18],"Shift":[19],"Register":[20],"(LFSR).":[21],"The":[22,34],"AM":[23],"is":[24],"applied":[25],"to":[26,48,58],"matrix-vector":[27],"multiplication":[28],"(MVM)":[29],"in":[30,37],"Neural":[31],"Networks":[32],"(NNs).":[33],"hardware":[35],"implementations":[36],"90nm":[38],"CMOS":[39],"technology":[40],"demonstrate":[41],"superior":[42],"power":[43],"and":[44,65],"area":[45],"efficiency":[46,64],"compared":[47],"state-of-the-art":[49],"designs.":[50],"Additionally,":[51],"study":[53],"explores":[54],"applying":[55],"stochastic":[56],"computing":[57],"LSTM":[59],"NNs,":[60],"showcasing":[61],"improved":[62],"energy":[63],"speed.":[66]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":6},{"year":2024,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}
