{"id":"https://openalex.org/W4388145415","doi":"https://doi.org/10.1109/lca.2023.3329443","title":"gem5-accel: A Pre-RTL Simulation Toolchain for Accelerator Architecture Validation","display_name":"gem5-accel: A Pre-RTL Simulation Toolchain for Accelerator Architecture Validation","publication_year":2023,"publication_date":"2023-11-01","ids":{"openalex":"https://openalex.org/W4388145415","doi":"https://doi.org/10.1109/lca.2023.3329443"},"language":"en","primary_location":{"id":"doi:10.1109/lca.2023.3329443","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lca.2023.3329443","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Architecture Letters","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5011363907","display_name":"Jo\u00e3o Vieira","orcid":"https://orcid.org/0000-0003-0038-2830"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]},{"id":"https://openalex.org/I141596103","display_name":"University of Lisbon","ror":"https://ror.org/01c27hj86","country_code":"PT","type":"education","lineage":["https://openalex.org/I141596103"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Jo\u00e3o Vieira","raw_affiliation_strings":["INESC-ID, Instituto Superior Técnico, University of Lisbon, Lisboa, Portugal"],"raw_orcid":"https://orcid.org/0000-0003-0038-2830","affiliations":[{"raw_affiliation_string":"INESC-ID, Instituto Superior Técnico, University of Lisbon, Lisboa, Portugal","institution_ids":["https://openalex.org/I121345201","https://openalex.org/I141596103"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015710714","display_name":"Nuno Roma","orcid":"https://orcid.org/0000-0003-2491-4977"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]},{"id":"https://openalex.org/I141596103","display_name":"University of Lisbon","ror":"https://ror.org/01c27hj86","country_code":"PT","type":"education","lineage":["https://openalex.org/I141596103"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Nuno Roma","raw_affiliation_strings":["INESC-ID, Instituto Superior Técnico, University of Lisbon, Lisboa, Portugal"],"raw_orcid":"https://orcid.org/0000-0003-2491-4977","affiliations":[{"raw_affiliation_string":"INESC-ID, Instituto Superior Técnico, University of Lisbon, Lisboa, Portugal","institution_ids":["https://openalex.org/I121345201","https://openalex.org/I141596103"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088848663","display_name":"Gabriel Falc\u00e3o","orcid":"https://orcid.org/0000-0001-9805-6747"},"institutions":[{"id":"https://openalex.org/I4210120471","display_name":"Instituto de Telecomunica\u00e7\u00f5es","ror":"https://ror.org/02ht4fk33","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I4210120471"]},{"id":"https://openalex.org/I76903346","display_name":"University of Coimbra","ror":"https://ror.org/04z8k9a98","country_code":"PT","type":"education","lineage":["https://openalex.org/I76903346"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Gabriel Falcao","raw_affiliation_strings":["Instituto de Telecomunicações, University of Coimbra, Coimbra, Portugal"],"raw_orcid":"https://orcid.org/0000-0001-9805-6747","affiliations":[{"raw_affiliation_string":"Instituto de Telecomunicações, University of Coimbra, Coimbra, Portugal","institution_ids":["https://openalex.org/I4210120471","https://openalex.org/I76903346"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5075054918","display_name":"Pedro Tom\u00e1s","orcid":"https://orcid.org/0000-0001-8083-4432"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]},{"id":"https://openalex.org/I141596103","display_name":"University of Lisbon","ror":"https://ror.org/01c27hj86","country_code":"PT","type":"education","lineage":["https://openalex.org/I141596103"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Pedro Tom\u00e1s","raw_affiliation_strings":["INESC-ID, Instituto Superior Técnico, University of Lisbon, Lisboa, Portugal"],"raw_orcid":"https://orcid.org/0000-0001-8083-4432","affiliations":[{"raw_affiliation_string":"INESC-ID, Instituto Superior Técnico, University of Lisbon, Lisboa, Portugal","institution_ids":["https://openalex.org/I121345201","https://openalex.org/I141596103"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.3856,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.88906856,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":97,"max":98},"biblio":{"volume":"23","issue":"1","first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9868000149726868,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/toolchain","display_name":"Toolchain","score":0.9970510601997375},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8477208614349365},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6261922121047974},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5110417604446411},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5081267356872559},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5001688003540039},{"id":"https://openalex.org/keywords/code-generation","display_name":"Code generation","score":0.4366007149219513},{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.41267138719558716},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.34412074089050293},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.23072421550750732},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.23064956068992615},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.17344823479652405}],"concepts":[{"id":"https://openalex.org/C2777062904","wikidata":"https://www.wikidata.org/wiki/Q545406","display_name":"Toolchain","level":3,"score":0.9970510601997375},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8477208614349365},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6261922121047974},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5110417604446411},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5081267356872559},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5001688003540039},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.4366007149219513},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.41267138719558716},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.34412074089050293},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.23072421550750732},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.23064956068992615},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.17344823479652405},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/lca.2023.3329443","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lca.2023.3329443","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Architecture Letters","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.4300000071525574,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W2147657366","https://openalex.org/W2150073849","https://openalex.org/W2170382128","https://openalex.org/W2771905466","https://openalex.org/W2946037574","https://openalex.org/W3011446983","https://openalex.org/W3106090013","https://openalex.org/W3213528054","https://openalex.org/W4249553981","https://openalex.org/W4301607055","https://openalex.org/W4312069181","https://openalex.org/W4313496512"],"related_works":["https://openalex.org/W2030503305","https://openalex.org/W3091557894","https://openalex.org/W2130241392","https://openalex.org/W2668012471","https://openalex.org/W4389166683","https://openalex.org/W4251625807","https://openalex.org/W3000490272","https://openalex.org/W4251692710","https://openalex.org/W2542439007","https://openalex.org/W3014988394"],"abstract_inverted_index":{"Attaining":[0],"the":[1,12,54,70,89],"performance":[2],"and":[3,30],"efficiency":[4],"levels":[5],"required":[6],"by":[7],"modern":[8],"applications":[9],"often":[10],"requires":[11],"use":[13],"of":[14,58,91],"application-specific":[15],"accelerators.":[16],"However,":[17],"writing":[18],"synthesizable":[19],"Register-Transfer":[20],"Level":[21],"code":[22],"for":[23,36],"such":[24],"accelerators":[25,60,94],"is":[26,34,49,73],"a":[27,45,77],"complex,":[28],"expensive,":[29],"time-consuming":[31],"process,":[32],"which":[33],"cumbersome":[35],"early":[37,55],"architecture":[38],"development":[39],"phases.":[40],"To":[41,66],"tackle":[42],"this":[43],"issue,":[44],"pre-synthesis":[46],"simulation":[47],"toolchain":[48],"herein":[50],"proposed":[51,71],"that":[52,84],"facilitates":[53],"architectural":[56],"evaluation":[57],"complex":[59,92],"aggregated":[61],"to":[62,75],"multi-level":[63],"memory":[64],"hierarchies.":[65],"demonstrate":[67],"its":[68],"usefulness,":[69],"gem5-accel":[72],"used":[74],"model":[76],"tensor":[78],"accelerator":[79],"based":[80],"on":[81],"Gemmini,":[82],"showing":[83],"it":[85],"can":[86],"successfully":[87],"anticipate":[88],"results":[90],"hardware":[93],"executing":[95],"deep":[96],"Neural":[97],"Networks.":[98]},"counts_by_year":[{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":5}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}