{"id":"https://openalex.org/W4311659433","doi":"https://doi.org/10.1109/lca.2022.3227643","title":"Advancing Compilation of DNNs for FPGAs Using Operation Set Architectures","display_name":"Advancing Compilation of DNNs for FPGAs Using Operation Set Architectures","publication_year":2022,"publication_date":"2022-12-13","ids":{"openalex":"https://openalex.org/W4311659433","doi":"https://doi.org/10.1109/lca.2022.3227643"},"language":"en","primary_location":{"id":"doi:10.1109/lca.2022.3227643","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lca.2022.3227643","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Architecture Letters","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://doi.org/10.1109/LCA.2022.3227643","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5042189622","display_name":"Burkhard Ringlein","orcid":"https://orcid.org/0000-0002-7222-9539"},"institutions":[{"id":"https://openalex.org/I4210126328","display_name":"IBM Research - Zurich","ror":"https://ror.org/02js37d36","country_code":"CH","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210126328"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Burkhard Ringlein","raw_affiliation_strings":["IBM Research Europe, Rüschlikon, Switzerland"],"raw_orcid":"https://orcid.org/0000-0002-7222-9539","affiliations":[{"raw_affiliation_string":"IBM Research Europe, Rüschlikon, Switzerland","institution_ids":["https://openalex.org/I4210126328"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103281184","display_name":"Fran\u00e7ois Abel","orcid":"https://orcid.org/0000-0002-3295-0292"},"institutions":[{"id":"https://openalex.org/I4210126328","display_name":"IBM Research - Zurich","ror":"https://ror.org/02js37d36","country_code":"CH","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210126328"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Francois Abel","raw_affiliation_strings":["IBM Research Europe, Rüschlikon, Switzerland"],"raw_orcid":"https://orcid.org/0000-0002-3295-0292","affiliations":[{"raw_affiliation_string":"IBM Research Europe, Rüschlikon, Switzerland","institution_ids":["https://openalex.org/I4210126328"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5055307805","display_name":"Dionysios Diamantopoulos","orcid":"https://orcid.org/0000-0003-2979-5946"},"institutions":[{"id":"https://openalex.org/I4210126328","display_name":"IBM Research - Zurich","ror":"https://ror.org/02js37d36","country_code":"CH","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210126328"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Dionysios Diamantopoulos","raw_affiliation_strings":["IBM Research Europe, Rüschlikon, Switzerland"],"raw_orcid":"https://orcid.org/0000-0003-2979-5946","affiliations":[{"raw_affiliation_string":"IBM Research Europe, Rüschlikon, Switzerland","institution_ids":["https://openalex.org/I4210126328"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080591951","display_name":"Beat Weiss","orcid":"https://orcid.org/0000-0002-4069-1286"},"institutions":[{"id":"https://openalex.org/I4210126328","display_name":"IBM Research - Zurich","ror":"https://ror.org/02js37d36","country_code":"CH","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210126328"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Beat Weiss","raw_affiliation_strings":["IBM Research Europe, Rüschlikon, Switzerland"],"raw_orcid":"https://orcid.org/0000-0002-4069-1286","affiliations":[{"raw_affiliation_string":"IBM Research Europe, Rüschlikon, Switzerland","institution_ids":["https://openalex.org/I4210126328"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001983294","display_name":"Christoph Hagleitner","orcid":"https://orcid.org/0000-0002-6815-7835"},"institutions":[{"id":"https://openalex.org/I4210126328","display_name":"IBM Research - Zurich","ror":"https://ror.org/02js37d36","country_code":"CH","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210126328"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Christoph Hagleitner","raw_affiliation_strings":["IBM Research Europe, Rüschlikon, Switzerland"],"raw_orcid":"https://orcid.org/0000-0002-6815-7835","affiliations":[{"raw_affiliation_string":"IBM Research Europe, Rüschlikon, Switzerland","institution_ids":["https://openalex.org/I4210126328"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030918623","display_name":"Dietmar Fey","orcid":"https://orcid.org/0000-0002-6077-4732"},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Dietmar Fey","raw_affiliation_strings":["Department of Computer Science, Friedrich-Alexander University Erlangen-Nürnberg, Erlangen, Germany"],"raw_orcid":"https://orcid.org/0000-0002-6077-4732","affiliations":[{"raw_affiliation_string":"Department of Computer Science, Friedrich-Alexander University Erlangen-Nürnberg, Erlangen, Germany","institution_ids":["https://openalex.org/I181369854"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.4351,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.59297162,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"22","issue":"1","first_page":"9","last_page":"12"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8199400901794434},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.794548511505127},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.791366696357727},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6275623440742493},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.560123860836029},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4626648426055908},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.37378162145614624},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3719610273838043},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3589646816253662},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10447001457214355},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.10437056422233582}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8199400901794434},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.794548511505127},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.791366696357727},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6275623440742493},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.560123860836029},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4626648426055908},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.37378162145614624},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3719610273838043},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3589646816253662},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10447001457214355},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.10437056422233582},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/lca.2022.3227643","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lca.2022.3227643","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Architecture Letters","raw_type":"journal-article"},{"id":"pmh:oai:zenodo.org:7446527","is_oa":true,"landing_page_url":"https://doi.org/10.1109/LCA.2022.3227643","pdf_url":null,"source":{"id":"https://openalex.org/S4306400562","display_name":"Zenodo (CERN European Organization for Nuclear Research)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I67311998","host_organization_name":"European Organization for Nuclear Research","host_organization_lineage":["https://openalex.org/I67311998"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Computer Architecture Letters, (2022-12-13)","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":{"id":"pmh:oai:zenodo.org:7446527","is_oa":true,"landing_page_url":"https://doi.org/10.1109/LCA.2022.3227643","pdf_url":null,"source":{"id":"https://openalex.org/S4306400562","display_name":"Zenodo (CERN European Organization for Nuclear Research)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I67311998","host_organization_name":"European Organization for Nuclear Research","host_organization_lineage":["https://openalex.org/I67311998"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Computer Architecture Letters, (2022-12-13)","raw_type":"info:eu-repo/semantics/article"},"sustainable_development_goals":[{"score":0.8100000023841858,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W2747844109","https://openalex.org/W2798084934","https://openalex.org/W2883929540","https://openalex.org/W2891946740","https://openalex.org/W2963114857","https://openalex.org/W2963568120","https://openalex.org/W2997106510","https://openalex.org/W3093982621","https://openalex.org/W3100220590","https://openalex.org/W3101493857","https://openalex.org/W3213111742","https://openalex.org/W3215210342"],"related_works":["https://openalex.org/W3096456556","https://openalex.org/W4240253816","https://openalex.org/W2169584677","https://openalex.org/W2979513934","https://openalex.org/W4232954277","https://openalex.org/W2020341030","https://openalex.org/W2749133591","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506"],"abstract_inverted_index":{"The":[0],"slow-down":[1],"of":[2,10,60,67,100,121],"technology":[3],"scaling":[4],"combined":[5],"with":[6,56],"the":[7,40,65,74,95,114],"exponential":[8],"growth":[9],"modern":[11],"machine":[12],"learning":[13],"and":[14,29,38,77,97],"artificial":[15],"intelligence":[16],"models":[17],"has":[18],"created":[19],"a":[20],"demand":[21],"for":[22],"specialized":[23,86],"accelerators,":[24,45],"such":[25],"as":[26],"GPUs,":[27],"ASICs,":[28],"field-programmable":[30],"gate":[31],"arrays":[32],"(FPGAs).":[33],"FPGAs":[34],"can":[35,112],"be":[36],"reconfigured":[37],"have":[39],"potential":[41],"to":[42,54,72],"outperform":[43],"other":[44],"while":[46],"also":[47,93],"being":[48],"more":[49,117],"energy-efficient,":[50],"but":[51],"are":[52],"cumbersome":[53],"use":[55],"today's":[57],"fractured":[58],"landscape":[59],"tool":[61],"flows.":[62],"We":[63],"propose":[64],"concept":[66],"an":[68,119],"operation":[69],"set":[70],"architecture":[71],"overcome":[73],"current":[75],"incompatibilities":[76],"hurdles":[78],"in":[79],"using":[80],"DNN-to-FPGA":[81],"compilers":[82],"by":[83,116],"combining":[84],"existing":[85,101,110],"frameworks":[87,111],"into":[88],"one":[89],"organic":[90],"compiler":[91],"that":[92,107],"allows":[94],"efficient":[96],"automatic":[98],"re-use":[99],"community":[102],"tools.":[103],"Furthermore,":[104],"we":[105],"demonstrate":[106],"mixing":[108],"different":[109],"increase":[113],"efficiency":[115],"than":[118],"order":[120],"magnitude.":[122]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}