{"id":"https://openalex.org/W3045328293","doi":"https://doi.org/10.1109/lca.2020.3011643","title":"pPIM: A Programmable Processor-in-Memory Architecture With Precision-Scaling for Deep Learning","display_name":"pPIM: A Programmable Processor-in-Memory Architecture With Precision-Scaling for Deep Learning","publication_year":2020,"publication_date":"2020-07-01","ids":{"openalex":"https://openalex.org/W3045328293","doi":"https://doi.org/10.1109/lca.2020.3011643","mag":"3045328293"},"language":"en","primary_location":{"id":"doi:10.1109/lca.2020.3011643","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lca.2020.3011643","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Architecture Letters","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5021789107","display_name":"Purab Ranjan Sutradhar","orcid":"https://orcid.org/0000-0003-3155-1115"},"institutions":[{"id":"https://openalex.org/I155173764","display_name":"Rochester Institute of Technology","ror":"https://ror.org/00v4yb702","country_code":"US","type":"education","lineage":["https://openalex.org/I155173764"]},{"id":"https://openalex.org/I157066012","display_name":"Gleason (United States)","ror":"https://ror.org/03bw04561","country_code":"US","type":"company","lineage":["https://openalex.org/I157066012"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Purab Ranjan Sutradhar","raw_affiliation_strings":["Rochester Institute of Technology Kate Gleason College of Engineering, Rochester, NY, USA"],"affiliations":[{"raw_affiliation_string":"Rochester Institute of Technology Kate Gleason College of Engineering, Rochester, NY, USA","institution_ids":["https://openalex.org/I157066012","https://openalex.org/I155173764"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031962103","display_name":"Mark Connolly","orcid":"https://orcid.org/0000-0002-3485-9812"},"institutions":[{"id":"https://openalex.org/I157066012","display_name":"Gleason (United States)","ror":"https://ror.org/03bw04561","country_code":"US","type":"company","lineage":["https://openalex.org/I157066012"]},{"id":"https://openalex.org/I155173764","display_name":"Rochester Institute of Technology","ror":"https://ror.org/00v4yb702","country_code":"US","type":"education","lineage":["https://openalex.org/I155173764"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mark Connolly","raw_affiliation_strings":["Rochester Institute of Technology Kate Gleason College of Engineering, Rochester, NY, USA"],"affiliations":[{"raw_affiliation_string":"Rochester Institute of Technology Kate Gleason College of Engineering, Rochester, NY, USA","institution_ids":["https://openalex.org/I157066012","https://openalex.org/I155173764"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073660180","display_name":"Sathwika Bavikadi","orcid":"https://orcid.org/0000-0002-1430-5070"},"institutions":[{"id":"https://openalex.org/I162714631","display_name":"George Mason University","ror":"https://ror.org/02jqj7156","country_code":"US","type":"education","lineage":["https://openalex.org/I162714631"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sathwika Bavikadi","raw_affiliation_strings":["Department of Electrical and Computer Engineering, George Mason University, Fairfax, VA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, George Mason University, Fairfax, VA, USA","institution_ids":["https://openalex.org/I162714631"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047725314","display_name":"Sai Manoj Pudukotai Dinakarrao","orcid":"https://orcid.org/0000-0002-4417-2387"},"institutions":[{"id":"https://openalex.org/I162714631","display_name":"George Mason University","ror":"https://ror.org/02jqj7156","country_code":"US","type":"education","lineage":["https://openalex.org/I162714631"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sai Manoj Pudukotai Dinakarrao","raw_affiliation_strings":["Department of Electrical and Computer Engineering, George Mason University, Fairfax, VA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, George Mason University, Fairfax, VA, USA","institution_ids":["https://openalex.org/I162714631"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047142572","display_name":"Mark Indovina","orcid":"https://orcid.org/0000-0002-6645-4596"},"institutions":[{"id":"https://openalex.org/I157066012","display_name":"Gleason (United States)","ror":"https://ror.org/03bw04561","country_code":"US","type":"company","lineage":["https://openalex.org/I157066012"]},{"id":"https://openalex.org/I155173764","display_name":"Rochester Institute of Technology","ror":"https://ror.org/00v4yb702","country_code":"US","type":"education","lineage":["https://openalex.org/I155173764"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mark A. Indovina","raw_affiliation_strings":["Rochester Institute of Technology Kate Gleason College of Engineering, Rochester, NY, USA"],"affiliations":[{"raw_affiliation_string":"Rochester Institute of Technology Kate Gleason College of Engineering, Rochester, NY, USA","institution_ids":["https://openalex.org/I157066012","https://openalex.org/I155173764"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5004368293","display_name":"Amlan Ganguly","orcid":"https://orcid.org/0000-0001-7354-7873"},"institutions":[{"id":"https://openalex.org/I157066012","display_name":"Gleason (United States)","ror":"https://ror.org/03bw04561","country_code":"US","type":"company","lineage":["https://openalex.org/I157066012"]},{"id":"https://openalex.org/I155173764","display_name":"Rochester Institute of Technology","ror":"https://ror.org/00v4yb702","country_code":"US","type":"education","lineage":["https://openalex.org/I155173764"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Amlan Ganguly","raw_affiliation_strings":["Rochester Institute of Technology Kate Gleason College of Engineering, Rochester, NY, USA"],"affiliations":[{"raw_affiliation_string":"Rochester Institute of Technology Kate Gleason College of Engineering, Rochester, NY, USA","institution_ids":["https://openalex.org/I157066012","https://openalex.org/I155173764"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5021789107"],"corresponding_institution_ids":["https://openalex.org/I155173764","https://openalex.org/I157066012"],"apc_list":null,"apc_paid":null,"fwci":2.2604,"has_fulltext":false,"cited_by_count":39,"citation_normalized_percentile":{"value":0.88480607,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":99},"biblio":{"volume":"19","issue":"2","first_page":"118","last_page":"121"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10036","display_name":"Advanced Neural Network Applications","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8533506989479065},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.6138900518417358},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5082475543022156},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.5016486644744873},{"id":"https://openalex.org/keywords/arithmetic-logic-unit","display_name":"Arithmetic logic unit","score":0.4731482267379761},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.44156602025032043},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4407762587070465},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3925171494483948},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3862575888633728}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8533506989479065},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.6138900518417358},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5082475543022156},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.5016486644744873},{"id":"https://openalex.org/C100276221","wikidata":"https://www.wikidata.org/wiki/Q192903","display_name":"Arithmetic logic unit","level":2,"score":0.4731482267379761},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.44156602025032043},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4407762587070465},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3925171494483948},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3862575888633728},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/lca.2020.3011643","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lca.2020.3011643","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Architecture Letters","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8799999952316284,"id":"https://metadata.un.org/sdg/7"}],"awards":[{"id":"https://openalex.org/G4079544850","display_name":null,"funder_award_id":"CNS-1553264","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W2170257519","https://openalex.org/W2332254524","https://openalex.org/W2611106620","https://openalex.org/W2765234579","https://openalex.org/W2766489088","https://openalex.org/W2777372517","https://openalex.org/W2801000640","https://openalex.org/W2809205380","https://openalex.org/W2946829484","https://openalex.org/W4292169167"],"related_works":["https://openalex.org/W2798215405","https://openalex.org/W2990962948","https://openalex.org/W2084169748","https://openalex.org/W2127529229","https://openalex.org/W2125609625","https://openalex.org/W2077105843","https://openalex.org/W2770465587","https://openalex.org/W4205690894","https://openalex.org/W2086716781","https://openalex.org/W2022510519"],"abstract_inverted_index":{"Memory":[0,30],"access":[1,45],"latencies":[2],"and":[3,155,185,205],"low":[4],"data":[5,14,44],"transfer":[6],"bandwidth":[7],"limit":[8],"the":[9,43,56,68,81,98,136,153,156,217,221],"processing":[10,65,99],"speed":[11],"of":[12,220],"many":[13],"intensive":[15],"applications":[16,41],"such":[17,40],"as":[18,34,42,106],"Convolutional":[19],"Neural":[20],"Networks":[21],"(CNNs)":[22],"in":[23,29,50,146,188],"conventional":[24,198],"Von":[25],"Neumann":[26],"architectures.":[27],"Processing":[28,202],"(PIM)":[31],"is":[32],"envisioned":[33],"a":[35,87,91,206],"potential":[36],"hardware":[37],"solution":[38],"for":[39,119,159,169],"bottlenecks":[46],"can":[47,181],"be":[48],"avoided":[49],"PIM":[51,60,89,95,111,211],"by":[52,224],"performing":[53],"computations":[54],"within":[55,67],"memory":[57,69,83],"die.":[58],"However,":[59],"realizations":[61],"with":[62,104,116,131],"logic-based":[63],"complex":[64],"units":[66,100],"present":[70],"complicated":[71],"fabrication":[72,133],"challenges.":[73],"In":[74],"this":[75],"letter,":[76],"we":[77],"propose":[78],"to":[79,85,108,124,196],"leverage":[80],"existing":[82],"infrastructure":[84],"implement":[86],"programmable":[88],"(pPIM),":[90],"novel":[92],"Look-Up-Table":[93],"(LUT)-based":[94],"where":[96],"all":[97],"are":[101],"implemented":[102],"solely":[103],"LUTs,":[105],"opposed":[107],"prior":[109,207],"LUT-based":[110,138],"implementations":[112],"that":[113,177],"combine":[114],"LUT":[115],"logic":[117],"circuitry":[118],"computations.":[120],"This":[121],"enables":[122],"pPIM":[123,180,222],"perform":[125],"ultra-low":[126],"power":[127,157,193],"&":[128],"low-latency":[129],"operations":[130],"minimal":[132],"complications.":[134],"Moreover,":[135],"complete":[137],"design":[139],"offers":[140],"simple":[141],"`memory":[142],"write'":[143],"based":[144,210],"programmability":[145,163],"pPIM.":[147],"Enabling":[148],"precision":[149,214],"scaling":[150,215],"further":[151],"improves":[152,216],"performance":[154],"consumption":[158,194],"CNN":[160],"applications.":[161],"The":[162],"feature":[164],"potentially":[165],"makes":[166],"it":[167],"easier":[168],"online":[170],"training":[171],"implementations.":[172],"Our":[173],"preliminary":[174],"simulations":[175],"demonstrate":[176],"our":[178],"proposed":[179],"achieve":[182],"2000x,":[183],"657.5x":[184],"1.46x":[186],"improvement":[187],"inference":[189],"throughput":[190],"per":[191],"unit":[192],"compared":[195],"state-of-the-art":[197],"processor":[199],"architecture,":[200],"Graphics":[201],"Unit":[203],"(GPUs)":[204],"hybrid":[208],"LUT-logic":[209],"respectively.":[212],"Furthermore,":[213],"energy":[218],"efficiency":[219],"approximately":[223],"1.35x":[225],"over":[226],"its":[227],"full-precision":[228],"operation.":[229]},"counts_by_year":[{"year":2025,"cited_by_count":7},{"year":2024,"cited_by_count":10},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":12},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}