{"id":"https://openalex.org/W2803022844","doi":"https://doi.org/10.1109/lca.2018.2827929","title":"Decoupled MapReduce for Shared-Memory Multi-Core Architectures","display_name":"Decoupled MapReduce for Shared-Memory Multi-Core Architectures","publication_year":2018,"publication_date":"2018-04-17","ids":{"openalex":"https://openalex.org/W2803022844","doi":"https://doi.org/10.1109/lca.2018.2827929","mag":"2803022844"},"language":"en","primary_location":{"id":"doi:10.1109/lca.2018.2827929","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lca.2018.2827929","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Architecture Letters","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006425693","display_name":"Konstantinos Iliakis","orcid":"https://orcid.org/0000-0002-1403-6851"},"institutions":[{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"Konstantinos Iliakis","raw_affiliation_strings":["National Technical University of Athens, Zografou, Greece"],"raw_orcid":"https://orcid.org/0000-0002-1403-6851","affiliations":[{"raw_affiliation_string":"National Technical University of Athens, Zografou, Greece","institution_ids":["https://openalex.org/I174458059"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076432415","display_name":"Sotirios Xydis","orcid":"https://orcid.org/0000-0003-3151-2730"},"institutions":[{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Sotirios Xydis","raw_affiliation_strings":["National Technical University of Athens, Zografou, Greece"],"raw_orcid":"https://orcid.org/0000-0003-3151-2730","affiliations":[{"raw_affiliation_string":"National Technical University of Athens, Zografou, Greece","institution_ids":["https://openalex.org/I174458059"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043131021","display_name":"Dimitrios Soudris","orcid":"https://orcid.org/0000-0002-6930-6847"},"institutions":[{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Dimitrios Soudris","raw_affiliation_strings":["National Technical University of Athens, Zografou, Greece"],"raw_orcid":"https://orcid.org/0000-0002-6930-6847","affiliations":[{"raw_affiliation_string":"National Technical University of Athens, Zografou, Greece","institution_ids":["https://openalex.org/I174458059"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5006425693"],"corresponding_institution_ids":["https://openalex.org/I174458059"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.05207896,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"17","issue":"2","first_page":"143","last_page":"146"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10101","display_name":"Cloud Computing and Resource Management","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10101","display_name":"Cloud Computing and Resource Management","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.907058596611023},{"id":"https://openalex.org/keywords/posix-threads","display_name":"POSIX Threads","score":0.7211306691169739},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6288433074951172},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.6090437769889832},{"id":"https://openalex.org/keywords/programming-paradigm","display_name":"Programming paradigm","score":0.5616618990898132},{"id":"https://openalex.org/keywords/distributed-shared-memory","display_name":"Distributed shared memory","score":0.4926014542579651},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.45964717864990234},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4435851275920868},{"id":"https://openalex.org/keywords/multithreading","display_name":"Multithreading","score":0.44270122051239014},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.43658214807510376},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.40586423873901367},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.38744857907295227},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.3161793351173401},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.2753336429595947},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.17472702264785767},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.1479949951171875}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.907058596611023},{"id":"https://openalex.org/C41138395","wikidata":"https://www.wikidata.org/wiki/Q928112","display_name":"POSIX Threads","level":3,"score":0.7211306691169739},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6288433074951172},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.6090437769889832},{"id":"https://openalex.org/C34165917","wikidata":"https://www.wikidata.org/wiki/Q188267","display_name":"Programming paradigm","level":2,"score":0.5616618990898132},{"id":"https://openalex.org/C39528615","wikidata":"https://www.wikidata.org/wiki/Q1229610","display_name":"Distributed shared memory","level":5,"score":0.4926014542579651},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.45964717864990234},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4435851275920868},{"id":"https://openalex.org/C201410400","wikidata":"https://www.wikidata.org/wiki/Q1064412","display_name":"Multithreading","level":3,"score":0.44270122051239014},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.43658214807510376},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.40586423873901367},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.38744857907295227},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.3161793351173401},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.2753336429595947},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.17472702264785767},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1479949951171875},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/lca.2018.2827929","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lca.2018.2827929","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Architecture Letters","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4099999964237213,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1982565841","https://openalex.org/W2005095133","https://openalex.org/W2033031014","https://openalex.org/W2046659665","https://openalex.org/W2054739713","https://openalex.org/W2060058231","https://openalex.org/W2068829602","https://openalex.org/W2103460560","https://openalex.org/W2104237323","https://openalex.org/W2104644701","https://openalex.org/W2139102017","https://openalex.org/W2139605600","https://openalex.org/W2173213060"],"related_works":["https://openalex.org/W990235011","https://openalex.org/W2398725611","https://openalex.org/W4285144448","https://openalex.org/W2140955407","https://openalex.org/W18986865","https://openalex.org/W1935251877","https://openalex.org/W32407979","https://openalex.org/W2163552442","https://openalex.org/W2126182039","https://openalex.org/W2033356227"],"abstract_inverted_index":{"Modern":[0],"multi-core":[1],"processors":[2],"exhibit":[3],"high":[4],"integration":[5],"densities,":[6],"e.g.,":[7,61],"up":[8,149],"to":[9,19,46,81,150,153],"several":[10],"tens":[11],"of":[12,23,39,49,96,126,148],"cores.":[13],"Multiple":[14],"programming":[15,29],"frameworks":[16],"have":[17],"emerged":[18],"facilitate":[20],"the":[21,37,47,68,74,93,124,127,142],"development":[22],"highly":[24],"parallel":[25,83],"applications.":[26],"The":[27,110],"MapReduce":[28,70,113,157],"model,":[30],"after":[31],"having":[32],"demonstrated":[33],"its":[34],"usability":[35],"in":[36,55,79,100],"area":[38],"distributed":[40],"computing":[41],"systems,":[42],"has":[43],"been":[44],"adapted":[45],"needs":[48],"shared-memory":[50,156],"multi-processors":[51],"showing":[52,122],"promising":[53],"results":[54],"comparison":[56],"with":[57],"conventional":[58],"multi-threaded":[59],"libraries,":[60],"pthreads.":[62],"In":[63],"this":[64],"paper":[65],"we":[66],"enhance":[67],"traditional":[69],"architecture":[71,114],"by":[72],"decoupling":[73],"map":[75],"and":[76,135],"combine":[77],"phases":[78],"order":[80],"boost":[82],"execution.":[84],"We":[85,139],"show":[86],"that":[87,123,141],"combiners'":[88],"memory":[89],"intensive":[90],"features":[91],"limit":[92],"system's":[94],"degree":[95],"parallelism,":[97],"thus":[98],"resulting":[99],"sub-optimal":[101],"hardware":[102,133],"utilization,":[103],"leaving":[104],"space":[105],"for":[106],"further":[107],"performance":[108],"improvements.":[109,138],"proposed":[111,143],"decoupled":[112],"is":[115],"evaluated":[116],"into":[117],"a":[118,154],"NUMA":[119],"server":[120],"platform,":[121],"adoption":[125],"De-MapR":[128],"runtime":[129],"enables":[130],"more":[131],"efficient":[132],"utilization":[134],"competent":[136],"run-time":[137],"demonstrate":[140],"solution":[144],"achieves":[145],"execution":[146],"speedups":[147],"2.46x":[151],"compared":[152],"state-of-the-art,":[155],"library.":[158]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
