{"id":"https://openalex.org/W2546844239","doi":"https://doi.org/10.1109/lca.2016.2623628","title":"A Scheme to Improve the Intrinsic Error Detection of the Instruction Set Architecture","display_name":"A Scheme to Improve the Intrinsic Error Detection of the Instruction Set Architecture","publication_year":2016,"publication_date":"2016-11-01","ids":{"openalex":"https://openalex.org/W2546844239","doi":"https://doi.org/10.1109/lca.2016.2623628","mag":"2546844239"},"language":"en","primary_location":{"id":"doi:10.1109/lca.2016.2623628","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lca.2016.2623628","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Architecture Letters","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5073710804","display_name":"Jorge Mart\u00ednez","orcid":"https://orcid.org/0000-0001-6014-248X"},"institutions":[{"id":"https://openalex.org/I3020445194","display_name":"Universidad Nebrija","ror":"https://ror.org/03tzyrt94","country_code":"ES","type":"education","lineage":["https://openalex.org/I3020445194"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"Jorge A. Martinez","raw_affiliation_strings":["Universidad Antonio de Nebrija, C/Pirineos, 55, Madrid 28040, Spain"],"raw_orcid":"https://orcid.org/0000-0001-6014-248X","affiliations":[{"raw_affiliation_string":"Universidad Antonio de Nebrija, C/Pirineos, 55, Madrid 28040, Spain","institution_ids":["https://openalex.org/I3020445194"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044495372","display_name":"Juan Antonio Maestro","orcid":"https://orcid.org/0000-0001-7133-9026"},"institutions":[{"id":"https://openalex.org/I3020445194","display_name":"Universidad Nebrija","ror":"https://ror.org/03tzyrt94","country_code":"ES","type":"education","lineage":["https://openalex.org/I3020445194"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Juan Antonio Maestro","raw_affiliation_strings":["Universidad Antonio de Nebrija, C/Pirineos, 55, Madrid 28040, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universidad Antonio de Nebrija, C/Pirineos, 55, Madrid 28040, Spain","institution_ids":["https://openalex.org/I3020445194"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5080322790","display_name":"Pedro Reviriego","orcid":"https://orcid.org/0000-0003-2540-5234"},"institutions":[{"id":"https://openalex.org/I3020445194","display_name":"Universidad Nebrija","ror":"https://ror.org/03tzyrt94","country_code":"ES","type":"education","lineage":["https://openalex.org/I3020445194"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Pedro Reviriego","raw_affiliation_strings":["Universidad Antonio de Nebrija, C/Pirineos, 55, Madrid 28040, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universidad Antonio de Nebrija, C/Pirineos, 55, Madrid 28040, Spain","institution_ids":["https://openalex.org/I3020445194"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5073710804"],"corresponding_institution_ids":["https://openalex.org/I3020445194"],"apc_list":null,"apc_paid":null,"fwci":1.4877,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.8457598,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"16","issue":"2","first_page":"103","last_page":"106"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/opcode","display_name":"Opcode","score":0.9408611059188843},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8530975580215454},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.7003074884414673},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.6625263690948486},{"id":"https://openalex.org/keywords/error-detection-and-correction","display_name":"Error detection and correction","score":0.6178804039955139},{"id":"https://openalex.org/keywords/parity-bit","display_name":"Parity bit","score":0.5946565270423889},{"id":"https://openalex.org/keywords/encoder","display_name":"Encoder","score":0.5823801755905151},{"id":"https://openalex.org/keywords/encoding","display_name":"Encoding (memory)","score":0.5754796862602234},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.4700036644935608},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.43817469477653503},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.42138856649398804},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4202638268470764},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.37144696712493896},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.34832727909088135},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09368181228637695},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.08644029498100281}],"concepts":[{"id":"https://openalex.org/C52173422","wikidata":"https://www.wikidata.org/wiki/Q766483","display_name":"Opcode","level":2,"score":0.9408611059188843},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8530975580215454},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.7003074884414673},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.6625263690948486},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.6178804039955139},{"id":"https://openalex.org/C131521367","wikidata":"https://www.wikidata.org/wiki/Q625502","display_name":"Parity bit","level":2,"score":0.5946565270423889},{"id":"https://openalex.org/C118505674","wikidata":"https://www.wikidata.org/wiki/Q42586063","display_name":"Encoder","level":2,"score":0.5823801755905151},{"id":"https://openalex.org/C125411270","wikidata":"https://www.wikidata.org/wiki/Q18653","display_name":"Encoding (memory)","level":2,"score":0.5754796862602234},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4700036644935608},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.43817469477653503},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.42138856649398804},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4202638268470764},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.37144696712493896},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.34832727909088135},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09368181228637695},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.08644029498100281},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/lca.2016.2623628","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lca.2016.2623628","pdf_url":null,"source":{"id":"https://openalex.org/S17643076","display_name":"IEEE Computer Architecture Letters","issn_l":"1556-6056","issn":["1556-6056","1556-6064","2473-2575"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Architecture Letters","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/4","display_name":"Quality Education","score":0.41999998688697815}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1974386611","https://openalex.org/W2055115253","https://openalex.org/W2083004950","https://openalex.org/W2099569658","https://openalex.org/W2118033476","https://openalex.org/W2165027640","https://openalex.org/W2165892937","https://openalex.org/W2174923727","https://openalex.org/W2253109415","https://openalex.org/W2555890549","https://openalex.org/W3149410719"],"related_works":["https://openalex.org/W2493009112","https://openalex.org/W2095590910","https://openalex.org/W1534272667","https://openalex.org/W3155621485","https://openalex.org/W3093226846","https://openalex.org/W2557040711","https://openalex.org/W4252066710","https://openalex.org/W4364295250","https://openalex.org/W2046374187","https://openalex.org/W2546844239"],"abstract_inverted_index":{"The":[0,55,122,166,183,224],"Instruction":[1],"Set":[2],"Architecture":[3],"(ISA)":[4],"determines":[5],"the":[6,18,25,66,92,114,126,129,135,140,164,172,188,212,215,221,227,234,244],"effect":[7],"that":[8,24,37,51,73,88,116,125,132,196],"a":[9,39,110,200],"soft":[10],"error":[11,130,245],"on":[12,17,71,233],"an":[13,43,49,53,100,241],"instruction":[14,41,45,50,222],"can":[15],"have":[16,22],"processor.":[19],"Previous":[20],"works":[21],"shown":[23],"ISA":[26,141,238],"has":[27,230],"some":[28],"intrinsic":[29],"capability":[30,247],"of":[31,57,113,139,186,214,226,248],"detecting":[32],"errors.":[33],"For":[34,68],"example,":[35,69],"errors":[36,59,70],"change":[38],"valid":[40],"into":[42,48],"invalid":[44],"encoding":[46,112],"or":[47,78,159,179,217],"causes":[52],"exception.":[54,101],"percentage":[56],"detectable":[58],"varies":[60],"widely":[61],"for":[62,76,91],"each":[63],"bit":[64,138],"in":[65,163,220,240,243],"ISA.":[67],"bits":[72,154],"are":[74,81,89,94,155,161,190,197],"used":[75,90],"immediate":[77],"register":[79],"values":[80],"unlikely":[82],"to":[83,97,99,148,199,207,250],"be":[84,149],"detected":[85],"while":[86],"those":[87],"opcode":[93],"more":[95,146],"likely":[96,147],"lead":[98],"In":[102],"this":[103,105],"paper,":[104],"is":[106,124,145,169,174,205],"exploited":[107],"by":[108],"introducing":[109],"simple":[111,191],"instructions":[115],"does":[117],"not":[118,175],"require":[119],"additional":[120,153],"bits.":[121],"idea":[123],"decoding":[127],"propagates":[128],"so":[131],"it":[133,144],"affects":[134],"most":[136],"sensitive":[137],"and":[142,193],"therefore":[143],"detected.":[150],"As":[151],"no":[152,157,210],"required,":[156],"changes":[158],"overheads":[160],"needed":[162],"memory.":[165],"proposed":[167,228],"scheme":[168,229],"useful":[170],"when":[171],"memory":[173],"protected":[176],"with":[177],"parity":[178,201],"Error":[180],"Correction":[181],"Codes.":[182],"only":[184],"cost":[185],"implementing":[187],"technique":[189,204],"encoder":[192],"decoder":[194],"circuits":[195],"similar":[198],"computation.":[202],"This":[203],"applicable":[206],"any":[208],"ISA,":[209],"matter":[211],"length":[213],"opcodes":[216],"their":[218],"location":[219],"encoding.":[223],"effectiveness":[225],"been":[231],"evaluated":[232],"ARM":[235],"Cortex":[236],"M0":[237],"resulting":[239],"increase":[242],"detection":[246],"up":[249],"1.64x.":[251]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":2}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}