{"id":"https://openalex.org/W2943740233","doi":"https://doi.org/10.1109/latw.2019.8704570","title":"IJTAG Compatible Delay-line based Voltage Embedded Instrument with One Clock-cycle Conversion Time","display_name":"IJTAG Compatible Delay-line based Voltage Embedded Instrument with One Clock-cycle Conversion Time","publication_year":2019,"publication_date":"2019-03-01","ids":{"openalex":"https://openalex.org/W2943740233","doi":"https://doi.org/10.1109/latw.2019.8704570","mag":"2943740233"},"language":"en","primary_location":{"id":"doi:10.1109/latw.2019.8704570","is_oa":false,"landing_page_url":"https://doi.org/10.1109/latw.2019.8704570","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE Latin American Test Symposium (LATS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5035049481","display_name":"Ghazanfar Ali","orcid":"https://orcid.org/0000-0001-5158-8236"},"institutions":[{"id":"https://openalex.org/I94624287","display_name":"University of Twente","ror":"https://ror.org/006hf6230","country_code":"NL","type":"education","lineage":["https://openalex.org/I94624287"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Ghazanfar Ali","raw_affiliation_strings":["Testable Design and Test of Integrated Systems (TDT) Group, CTIT Research Institute, University of Twente, Enschede, the Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Testable Design and Test of Integrated Systems (TDT) Group, CTIT Research Institute, University of Twente, Enschede, the Netherlands","institution_ids":["https://openalex.org/I94624287"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036815612","display_name":"Jerrin Pathrose","orcid":null},"institutions":[{"id":"https://openalex.org/I94624287","display_name":"University of Twente","ror":"https://ror.org/006hf6230","country_code":"NL","type":"education","lineage":["https://openalex.org/I94624287"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Jerrin Pathrose","raw_affiliation_strings":["Testable Design and Test of Integrated Systems (TDT) Group, CTIT Research Institute, University of Twente, Enschede, the Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Testable Design and Test of Integrated Systems (TDT) Group, CTIT Research Institute, University of Twente, Enschede, the Netherlands","institution_ids":["https://openalex.org/I94624287"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063280452","display_name":"Hans G. Kerkhoff","orcid":null},"institutions":[{"id":"https://openalex.org/I94624287","display_name":"University of Twente","ror":"https://ror.org/006hf6230","country_code":"NL","type":"education","lineage":["https://openalex.org/I94624287"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Hans G. Kerkhoff","raw_affiliation_strings":["Testable Design and Test of Integrated Systems (TDT) Group, CTIT Research Institute, University of Twente, Enschede, the Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Testable Design and Test of Integrated Systems (TDT) Group, CTIT Research Institute, University of Twente, Enschede, the Netherlands","institution_ids":["https://openalex.org/I94624287"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.6055,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.68445624,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dependability","display_name":"Dependability","score":0.8996897339820862},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5854356288909912},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.573035478591919},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.45037639141082764},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.44965600967407227},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.4396684169769287},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.42091989517211914},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4173109233379364},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.41628116369247437},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.3685835003852844},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.36131414771080017},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25346940755844116},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.21979689598083496},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.17240086197853088}],"concepts":[{"id":"https://openalex.org/C77019957","wikidata":"https://www.wikidata.org/wiki/Q2689057","display_name":"Dependability","level":2,"score":0.8996897339820862},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5854356288909912},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.573035478591919},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.45037639141082764},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.44965600967407227},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.4396684169769287},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.42091989517211914},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4173109233379364},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.41628116369247437},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.3685835003852844},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.36131414771080017},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25346940755844116},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.21979689598083496},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.17240086197853088},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/latw.2019.8704570","is_oa":false,"landing_page_url":"https://doi.org/10.1109/latw.2019.8704570","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE Latin American Test Symposium (LATS)","raw_type":"proceedings-article"},{"id":"pmh:oai:ris.utwente.nl:openaire_cris_publications/249f80ed-21b4-4c5d-83d8-b910e317f686","is_oa":false,"landing_page_url":"https://research.utwente.nl/en/publications/249f80ed-21b4-4c5d-83d8-b910e317f686","pdf_url":null,"source":{"id":"https://openalex.org/S4406922991","display_name":"University of Twente Research Information","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Ali, G, Pathrose Vareed, J & Kerkhoff, H G 2019, IJTAG Compatible Delay-line based Voltage Embedded Instrument with One Clock-cycle Conversion Time. in 2019 IEEE Latin American Test Symposium (LATS)., 8704570, 20th IEEE Latin American Test Symposium 2019, Santiago, Chile, 11/03/19. https://doi.org/10.1109/LATW.2019.8704570","raw_type":"info:eu-repo/semantics/publishedVersion"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8100000023841858,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320314237","display_name":"Rijksdienst voor Ondernemend Nederland","ror":null},{"id":"https://openalex.org/F4320327207","display_name":"Electronic Components and Systems for European Leadership","ror":null}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1584309135","https://openalex.org/W2015917466","https://openalex.org/W2064189791","https://openalex.org/W2065430789","https://openalex.org/W2096661249","https://openalex.org/W2102352834","https://openalex.org/W2170333286","https://openalex.org/W2317523264","https://openalex.org/W2588150542","https://openalex.org/W2799265834","https://openalex.org/W2810494848","https://openalex.org/W2889347940","https://openalex.org/W2901192426","https://openalex.org/W4243047118"],"related_works":["https://openalex.org/W2116514610","https://openalex.org/W1991670063","https://openalex.org/W4242565052","https://openalex.org/W2999907514","https://openalex.org/W2003180247","https://openalex.org/W2074584731","https://openalex.org/W1514283284","https://openalex.org/W2147289961","https://openalex.org/W2523953375","https://openalex.org/W2115980617"],"abstract_inverted_index":{"The":[0,120],"monitoring":[1],"of":[2,65,107,137,144],"critical-paths":[3],"in":[4,69],"Systems-on-Chip":[5],"to":[6,38,50,80,88,116,152],"ensure":[7],"dependable":[8],"operation":[9],"during":[10],"the":[11,21,40,52,62,82,90,117,129,138],"lifetime":[12,28],"is":[13,48,155],"becoming":[14],"essential":[15],"for":[16,86,157],"safety-critical":[17],"applications.":[18,160],"Based":[19],"on":[20],"timing":[22,68,84],"information,":[23],"different":[24],"procedures":[25],"like":[26,56],"remaining":[27,91],"prediction,":[29],"voltage,":[30],"and":[31,59],"frequency":[32],"scaling":[33],"can":[34],"be":[35],"carried":[36],"out":[37],"retain":[39],"desired":[41],"functionality.":[42],"To":[43],"perform":[44],"these":[45],"operations,":[46],"it":[47],"important":[49],"measure":[51],"run-time":[53],"changing":[54],"parameters":[55],"operating":[57],"voltage":[58,100],"temperature,":[60],"at":[61],"same":[63],"moment":[64],"measuring":[66,81],"slack-delay":[67,83],"critical":[70],"paths.":[71],"This":[72,93],"will":[73],"provide":[74],"a":[75,96,104,142,147],"better":[76],"correlation,":[77],"as":[78],"compared":[79],"alone,":[85],"instance,":[87],"determine":[89],"lifetime.":[92],"paper":[94],"presents":[95],"novel":[97],"delay-line":[98],"based":[99],"embedded":[101,122],"instrument":[102,123],"with":[103,113,146],"conversion":[105],"time":[106],"just":[108],"one":[109],"clock":[110],"cycle":[111],"along":[112],"its":[114],"integration":[115],"IJTAG":[118],"network.":[119],"proposed":[121,139],"(EI)":[124],"has":[125],"been":[126],"designed":[127],"using":[128],"TSMC":[130],"40nm":[131],"standard":[132],"cell":[133],"library.":[134],"Simulation":[135],"results":[136],"EI":[140],"show":[141],"resolution":[143],"10mV":[145],"detection":[148],"range":[149],"from":[150],"0.95V":[151],"1.20V,":[153],"which":[154],"sufficient":[156],"most":[158],"dependability":[159]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
