{"id":"https://openalex.org/W2798742041","doi":"https://doi.org/10.1109/latw.2018.8349688","title":"Superimposed in-circuit debugging for self-healing FPGA overlays","display_name":"Superimposed in-circuit debugging for self-healing FPGA overlays","publication_year":2018,"publication_date":"2018-03-01","ids":{"openalex":"https://openalex.org/W2798742041","doi":"https://doi.org/10.1109/latw.2018.8349688","mag":"2798742041"},"language":"en","primary_location":{"id":"doi:10.1109/latw.2018.8349688","is_oa":false,"landing_page_url":"https://doi.org/10.1109/latw.2018.8349688","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE 19th Latin-American Test Symposium (LATS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037198657","display_name":"Alexandra Kourfali","orcid":"https://orcid.org/0000-0003-3430-1007"},"institutions":[{"id":"https://openalex.org/I32597200","display_name":"Ghent University","ror":"https://ror.org/00cv9y106","country_code":"BE","type":"education","lineage":["https://openalex.org/I32597200"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Alexandra Kourfali","raw_affiliation_strings":["Department of Electronics and Information Systems (ELIS), Ghent University iGent, Ghent, Belgium"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Information Systems (ELIS), Ghent University iGent, Ghent, Belgium","institution_ids":["https://openalex.org/I32597200"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5004502321","display_name":"Dirk Stroobandt","orcid":"https://orcid.org/0000-0002-4477-5313"},"institutions":[{"id":"https://openalex.org/I32597200","display_name":"Ghent University","ror":"https://ror.org/00cv9y106","country_code":"BE","type":"education","lineage":["https://openalex.org/I32597200"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Dirk Stroobandt","raw_affiliation_strings":["Department of Electronics and Information Systems (ELIS), Ghent University iGent, Ghent, Belgium"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Information Systems (ELIS), Ghent University iGent, Ghent, Belgium","institution_ids":["https://openalex.org/I32597200"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I32597200"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9958999752998352,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.8974772095680237},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8134610652923584},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7838616371154785},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.6972047686576843},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6449609398841858},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6431852579116821},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5110589265823364},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3435460329055786},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.18723845481872559}],"concepts":[{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.8974772095680237},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8134610652923584},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7838616371154785},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.6972047686576843},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6449609398841858},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6431852579116821},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5110589265823364},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3435460329055786},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.18723845481872559},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/latw.2018.8349688","is_oa":false,"landing_page_url":"https://doi.org/10.1109/latw.2018.8349688","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE 19th Latin-American Test Symposium (LATS)","raw_type":"proceedings-article"},{"id":"pmh:oai:archive.ugent.be:8583679","is_oa":false,"landing_page_url":"https://biblio.ugent.be/publication/8583679","pdf_url":null,"source":{"id":"https://openalex.org/S4306400478","display_name":"Ghent University Academic Bibliography (Ghent University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I32597200","host_organization_name":"Ghent University","host_organization_lineage":["https://openalex.org/I32597200"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"ISBN: 9781538614723","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6399999856948853,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[{"id":"https://openalex.org/G2879175600","display_name":"Exploiting eXascale Technology with Reconfigurable Architectures","funder_award_id":"671653","funder_id":"https://openalex.org/F4320320300","funder_display_name":"European Commission"},{"id":"https://openalex.org/G4937468798","display_name":null,"funder_award_id":"H2020","funder_id":"https://openalex.org/F4320320300","funder_display_name":"European Commission"},{"id":"https://openalex.org/G6527945561","display_name":null,"funder_award_id":"671653","funder_id":"https://openalex.org/F4320332999","funder_display_name":"Horizon 2020 Framework Programme"}],"funders":[{"id":"https://openalex.org/F4320320300","display_name":"European Commission","ror":"https://ror.org/00k4n6c32"},{"id":"https://openalex.org/F4320321730","display_name":"Fonds Wetenschappelijk Onderzoek","ror":"https://ror.org/03qtxy027"},{"id":"https://openalex.org/F4320332999","display_name":"Horizon 2020 Framework Programme","ror":"https://ror.org/00k4n6c32"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1572929635","https://openalex.org/W2005602803","https://openalex.org/W2017517691","https://openalex.org/W2025907248","https://openalex.org/W2124870639","https://openalex.org/W2463602245","https://openalex.org/W2554510265","https://openalex.org/W2611861036","https://openalex.org/W2963186836","https://openalex.org/W6737626253"],"related_works":["https://openalex.org/W4321442002","https://openalex.org/W2015265939","https://openalex.org/W2284072287","https://openalex.org/W2611067230","https://openalex.org/W2480201319","https://openalex.org/W2387706296","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2038503502"],"abstract_inverted_index":{"Field":[0],"Programmable":[1],"Gate":[2],"Arrays":[3],"(FPGAs)":[4],"gain":[5],"popularity":[6],"as":[7,134],"higher-level":[8],"tools":[9,35,132],"evolve":[10],"to":[11,18,29,56,79,139],"deliver":[12],"the":[13,42],"benefits":[14],"of":[15,25,45,60,71,113,149],"reprogrammable":[16],"silicon":[17],"engineers":[19],"and":[20,36,82,100,111,117,142],"scientists":[21],"at":[22],"all":[23],"levels":[24],"expertise.":[26],"In":[27,85],"order":[28],"use":[30,148],"FPGAs":[31],"efficiently,":[32],"new":[33],"CAD":[34,131],"modern":[37],"architectures":[38,50,73,145],"are":[39],"needed":[40],"for":[41],"growing":[43],"demands":[44],"heterogeneous":[46,66],"computing":[47,62,67],"paradigms.":[48],"Overlay":[49],"have":[51],"become":[52],"a":[53,58,90],"popular":[54],"option":[55],"support":[57],"variety":[59],"high-performance":[61],"applications":[63],"implemented":[64],"on":[65,125],"platforms.":[68],"However,":[69],"most":[70],"these":[72],"cannot":[74],"offer":[75],"an":[76],"efficient":[77],"way":[78],"dynamically":[80],"debug":[81,99,141],"repair":[83,143],"them.":[84],"this":[86],"paper,":[87],"we":[88],"propose":[89],"superimposed":[91],"virtual":[92,144],"coarse-grained":[93],"reconfigurable":[94],"architecture,":[95],"embedded":[96],"with":[97,146],"on-demand":[98],"self-healing":[101],"capabilities.":[102],"The":[103,120],"proposed":[104],"architecture":[105],"supports":[106],"flexible":[107],"in-circuit":[108],"error":[109],"detection":[110],"correction":[112],"generic":[114],"Processing":[115],"Elements":[116],"Virtual":[118],"Channels.":[119],"debugging":[121],"infrastructure":[122],"is":[123],"constructed":[124],"resources":[126],"released":[127],"by":[128],"custom":[129],"tailor-made":[130],"(such":[133],"parameterised":[135],"configuration),":[136],"making":[137],"feasible":[138],"rapidly":[140],"minimal":[147],"additional":[150],"FPGA":[151],"resources.":[152]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}