{"id":"https://openalex.org/W2798590839","doi":"https://doi.org/10.1109/latw.2018.8349666","title":"Flexible architecture of memory BISTs","display_name":"Flexible architecture of memory BISTs","publication_year":2018,"publication_date":"2018-03-01","ids":{"openalex":"https://openalex.org/W2798590839","doi":"https://doi.org/10.1109/latw.2018.8349666","mag":"2798590839"},"language":"en","primary_location":{"id":"doi:10.1109/latw.2018.8349666","is_oa":false,"landing_page_url":"https://doi.org/10.1109/latw.2018.8349666","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE 19th Latin-American Test Symposium (LATS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067831437","display_name":"Reinaldo Silveira","orcid":null},"institutions":[{"id":"https://openalex.org/I1334877674","display_name":"Taiwan Semiconductor Manufacturing Company (United States)","ror":"https://ror.org/02rvfjx92","country_code":"US","type":"company","lineage":["https://openalex.org/I1334877674","https://openalex.org/I4210120917"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Reinaldo Silveira","raw_affiliation_strings":["Memory Test and Repair Team at NXP Semiconductors Corp Campinas, Brazil, Austin, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Memory Test and Repair Team at NXP Semiconductors Corp Campinas, Brazil, Austin, USA","institution_ids":["https://openalex.org/I1334877674"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078769299","display_name":"Qadeer Qureshi","orcid":null},"institutions":[{"id":"https://openalex.org/I1334877674","display_name":"Taiwan Semiconductor Manufacturing Company (United States)","ror":"https://ror.org/02rvfjx92","country_code":"US","type":"company","lineage":["https://openalex.org/I1334877674","https://openalex.org/I4210120917"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Qadeer Qureshi","raw_affiliation_strings":["Memory Test and Repair Team at NXP Semiconductors Corp Campinas, Brazil, Austin, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Memory Test and Repair Team at NXP Semiconductors Corp Campinas, Brazil, Austin, USA","institution_ids":["https://openalex.org/I1334877674"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5004884319","display_name":"Rodrigo Zeli","orcid":null},"institutions":[{"id":"https://openalex.org/I1334877674","display_name":"Taiwan Semiconductor Manufacturing Company (United States)","ror":"https://ror.org/02rvfjx92","country_code":"US","type":"company","lineage":["https://openalex.org/I1334877674","https://openalex.org/I4210120917"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rodrigo Zeli","raw_affiliation_strings":["Memory Test and Repair Team at NXP Semiconductors Corp Campinas, Brazil, Austin, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Memory Test and Repair Team at NXP Semiconductors Corp Campinas, Brazil, Austin, USA","institution_ids":["https://openalex.org/I1334877674"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.9502,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.74746193,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13293","display_name":"Engineering and Test Systems","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8507683277130127},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.6133159399032593},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.5201842784881592},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4882519543170929},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4450127184391022},{"id":"https://openalex.org/keywords/scripting-language","display_name":"Scripting language","score":0.43533855676651},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.42817503213882446},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.42384690046310425},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3939882814884186},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.36669981479644775},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.07306289672851562}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8507683277130127},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.6133159399032593},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.5201842784881592},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4882519543170929},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4450127184391022},{"id":"https://openalex.org/C61423126","wikidata":"https://www.wikidata.org/wiki/Q187432","display_name":"Scripting language","level":2,"score":0.43533855676651},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.42817503213882446},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.42384690046310425},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3939882814884186},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36669981479644775},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.07306289672851562},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/latw.2018.8349666","is_oa":false,"landing_page_url":"https://doi.org/10.1109/latw.2018.8349666","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE 19th Latin-American Test Symposium (LATS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W289624287","https://openalex.org/W2005160252","https://openalex.org/W2084117299","https://openalex.org/W2117936236","https://openalex.org/W2152959934","https://openalex.org/W2153093281"],"related_works":["https://openalex.org/W2143690511","https://openalex.org/W2096506606","https://openalex.org/W1510408562","https://openalex.org/W1959889508","https://openalex.org/W2145484885","https://openalex.org/W2001585562","https://openalex.org/W1970751325","https://openalex.org/W2105031241","https://openalex.org/W3163143851","https://openalex.org/W2049272650"],"abstract_inverted_index":{"This":[0],"paper":[1],"will":[2],"present":[3],"a":[4],"flexible":[5],"Memory":[6],"Built-in":[7],"Self-Test":[8],"(MBIST)":[9],"designed":[10],"to":[11,15,36,52],"be":[12,50],"easily":[13],"adaptable":[14],"specific":[16],"memory":[17],"configurations":[18],"and":[19],"user":[20],"requirements.":[21],"Its":[22],"RTL":[23],"code":[24,38],"is":[25],"generated":[26],"by":[27],"means":[28],"of":[29,42,55],"programming":[30],"scripts":[31],"that":[32],"provide":[33],"an":[34],"easy":[35],"read":[37],"without":[39],"the":[40,63,72,78],"use":[41],"complex":[43],"compiler":[44],"directives.":[45],"The":[46],"basic":[47],"architecture":[48],"can":[49],"adapted":[51],"different":[53],"schemes":[54],"test":[56],"such":[57],"as":[58],"parallel,":[59],"in":[60,70],"which":[61,71],"all":[62],"memories":[64,73],"are":[65,74],"tested":[66,75],"concurrently,":[67],"or":[68],"sequential,":[69],"one":[76],"at":[77],"time.":[79]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":7},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}