{"id":"https://openalex.org/W2607819469","doi":"https://doi.org/10.1109/latw.2017.7906757","title":"Identifying high variability speed-limiting paths under aging","display_name":"Identifying high variability speed-limiting paths under aging","publication_year":2017,"publication_date":"2017-03-01","ids":{"openalex":"https://openalex.org/W2607819469","doi":"https://doi.org/10.1109/latw.2017.7906757","mag":"2607819469"},"language":"en","primary_location":{"id":"doi:10.1109/latw.2017.7906757","is_oa":false,"landing_page_url":"https://doi.org/10.1109/latw.2017.7906757","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 18th IEEE Latin American Test Symposium (LATS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5045026834","display_name":"Ankush Srivastava","orcid":"https://orcid.org/0000-0002-7894-3952"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Ankush Srivastava","raw_affiliation_strings":["Indian Institute of Technology, Bombay, India","NXP Semiconductor India Pvt Ltd, Noida, India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology, Bombay, India","institution_ids":["https://openalex.org/I162827531"]},{"raw_affiliation_string":"NXP Semiconductor India Pvt Ltd, Noida, India","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073587430","display_name":"Virendra Singh","orcid":"https://orcid.org/0000-0002-7035-7844"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Virendra Singh","raw_affiliation_strings":["Indian Institute of Technology, Bombay, India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology, Bombay, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5104362993","display_name":"Adit D. Singh","orcid":null},"institutions":[{"id":"https://openalex.org/I82497590","display_name":"Auburn University","ror":"https://ror.org/02v80fc35","country_code":"US","type":"education","lineage":["https://openalex.org/I82497590"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Adit D Singh","raw_affiliation_strings":["Auburn University, AL, USA"],"affiliations":[{"raw_affiliation_string":"Auburn University, AL, USA","institution_ids":["https://openalex.org/I82497590"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110218098","display_name":"Kewal K. Saluja","orcid":null},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kewal K Saluja","raw_affiliation_strings":["University of Wisconsin, Madison, WI, USA"],"affiliations":[{"raw_affiliation_string":"University of Wisconsin, Madison, WI, USA","institution_ids":["https://openalex.org/I135310074"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5045026834"],"corresponding_institution_ids":["https://openalex.org/I162827531"],"apc_list":null,"apc_paid":null,"fwci":0.1433,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.48112317,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/monte-carlo-method","display_name":"Monte Carlo method","score":0.8070824146270752},{"id":"https://openalex.org/keywords/limiting","display_name":"Limiting","score":0.7220218181610107},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.6712862253189087},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6227273344993591},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.6181942224502563},{"id":"https://openalex.org/keywords/negative-bias-temperature-instability","display_name":"Negative-bias temperature instability","score":0.6010740995407104},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.5932685136795044},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.5908594131469727},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.47712278366088867},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3429146409034729},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.17931458353996277},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1755017638206482},{"id":"https://openalex.org/keywords/statistics","display_name":"Statistics","score":0.16856148838996887},{"id":"https://openalex.org/keywords/mosfet","display_name":"MOSFET","score":0.10310304164886475},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.09684184193611145}],"concepts":[{"id":"https://openalex.org/C19499675","wikidata":"https://www.wikidata.org/wiki/Q232207","display_name":"Monte Carlo method","level":2,"score":0.8070824146270752},{"id":"https://openalex.org/C188198153","wikidata":"https://www.wikidata.org/wiki/Q1613840","display_name":"Limiting","level":2,"score":0.7220218181610107},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.6712862253189087},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6227273344993591},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.6181942224502563},{"id":"https://openalex.org/C557185","wikidata":"https://www.wikidata.org/wiki/Q6987194","display_name":"Negative-bias temperature instability","level":5,"score":0.6010740995407104},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.5932685136795044},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.5908594131469727},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.47712278366088867},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3429146409034729},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.17931458353996277},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1755017638206482},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.16856148838996887},{"id":"https://openalex.org/C2778413303","wikidata":"https://www.wikidata.org/wiki/Q210793","display_name":"MOSFET","level":4,"score":0.10310304164886475},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.09684184193611145},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/latw.2017.7906757","is_oa":false,"landing_page_url":"https://doi.org/10.1109/latw.2017.7906757","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 18th IEEE Latin American Test Symposium (LATS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.4099999964237213,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1629355038","https://openalex.org/W2025670213","https://openalex.org/W2049623203","https://openalex.org/W2102729267","https://openalex.org/W2133807254","https://openalex.org/W2135132351","https://openalex.org/W2136500761","https://openalex.org/W2142047886","https://openalex.org/W2156770737","https://openalex.org/W2167021379","https://openalex.org/W2170333286","https://openalex.org/W2293258669","https://openalex.org/W6685176031"],"related_works":["https://openalex.org/W2365007040","https://openalex.org/W1970519101","https://openalex.org/W4235807419","https://openalex.org/W2045633099","https://openalex.org/W2144633290","https://openalex.org/W1910575119","https://openalex.org/W2550704533","https://openalex.org/W2890026549","https://openalex.org/W2827496155","https://openalex.org/W4233474994"],"abstract_inverted_index":{"Negative":[0],"bias":[1],"temperature":[2],"instability":[3],"(NBTI)":[4],"is":[5,27,144],"a":[6,28,67],"key":[7],"reliability":[8],"issue":[9],"in":[10,22,72,111],"deep":[11],"sub-micron":[12],"technology":[13],"nodes.":[14],"Identifying":[15],"NBTI":[16],"induced":[17],"high":[18,74],"variability":[19,75],"timing-critical":[20,76],"paths":[21,77],"stipulated":[23],"design":[24],"cycle":[25],"time":[26,106],"real":[29],"challenge":[30],"for":[31],"System-on-Chip":[32],"(SoC)":[33],"designers.":[34],"Firstly,":[35],"we":[36,85,138],"identify":[37],"those":[38],"device":[39],"parameters":[40],"that":[41,70,98,118,140],"must":[42],"be":[43],"considered":[44],"while":[45],"performing":[46],"statistical":[47,62],"simulations":[48],"to":[49,82],"estimate":[50],"maximum":[51],"path":[52,120,133],"delays":[53,121],"under":[54,78],"operational":[55],"aging.":[56],"By":[57],"using":[58,90,96],"the":[59,87,91,119,124,136,141,150],"results":[60,116],"of":[61,89,95],"simulations,":[63],"this":[64],"paper":[65],"proposes":[66],"segment-based":[68],"approach":[69],"helps":[71],"identifying":[73,112],"asymmetric":[79],"aging":[80],"due":[81],"NBTI.":[83],"Secondly,":[84],"explore":[86],"possibility":[88],"proposed":[92,125,142],"procedure":[93,126,143],"instead":[94],"methodologies":[97],"involve":[99],"worse-case":[100],"static":[101],"timing":[102],"analysis":[103],"(STA)":[104],"and":[105],"expensive":[107],"Monte-Carlo":[108,131],"(MC)":[109],"simulation":[110],"speed-limiting":[113],"paths.":[114],"Experimental":[115],"show":[117],"estimated":[122,132],"by":[123],"have":[127],"strong":[128],"correlation":[129],"with":[130],"delays.":[134],"At":[135],"end,":[137],"demonstrate":[139],"approx":[145],"1.4":[146],"times":[147],"faster":[148],"than":[149],"traditional":[151],"MC":[152],"simulations.":[153]},"counts_by_year":[{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
