{"id":"https://openalex.org/W2408850501","doi":"https://doi.org/10.1109/latw.2016.7483353","title":"On-silicon validation of a benchmark generation methodology for effectively evaluating combinational cell library design","display_name":"On-silicon validation of a benchmark generation methodology for effectively evaluating combinational cell library design","publication_year":2016,"publication_date":"2016-04-01","ids":{"openalex":"https://openalex.org/W2408850501","doi":"https://doi.org/10.1109/latw.2016.7483353","mag":"2408850501"},"language":"en","primary_location":{"id":"doi:10.1109/latw.2016.7483353","is_oa":false,"landing_page_url":"https://doi.org/10.1109/latw.2016.7483353","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 17th Latin-American Test Symposium (LATS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101437140","display_name":"Maur\u00edcio Carvalho","orcid":"https://orcid.org/0000-0002-6314-7099"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"M. De Carvalho","raw_affiliation_strings":["Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028387098","display_name":"Mauricio Altieri","orcid":null},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"M. Altieri","raw_affiliation_strings":["Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038283387","display_name":"Lauro Scheffer Puricelli","orcid":null},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"L. Puricelli","raw_affiliation_strings":["Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062131940","display_name":"Paulo F. Butzen","orcid":"https://orcid.org/0000-0003-1587-7596"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"P. Butzen","raw_affiliation_strings":["Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090563366","display_name":"Renato P. Ribas","orcid":"https://orcid.org/0000-0002-9895-7489"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"R. P. Ribas","raw_affiliation_strings":["Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081525917","display_name":"Eric Fabris","orcid":"https://orcid.org/0000-0003-3313-4059"},"institutions":[{"id":"https://openalex.org/I126460647","display_name":"Universidade Federal do Rio Grande","ror":"https://ror.org/05hpfkn88","country_code":"BR","type":"education","lineage":["https://openalex.org/I126460647"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"E. Fabris","raw_affiliation_strings":["Federal University of Rio Grande (FURG), Rio Grande, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Federal University of Rio Grande (FURG), Rio Grande, Brazil","institution_ids":["https://openalex.org/I126460647"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"135","last_page":"140"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.8091185092926025},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.7327317595481873},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6382424831390381},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.6253129839897156},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6164035797119141},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4914284944534302},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.47174322605133057},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.4620238244533539},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.4573712646961212},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.447786420583725},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4214667081832886},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.36411046981811523},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.35678431391716003},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.3072059750556946},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.28201329708099365},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.26052284240722656},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.24416884779930115},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1077432930469513},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.0951763391494751},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.09464475512504578}],"concepts":[{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.8091185092926025},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.7327317595481873},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6382424831390381},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.6253129839897156},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6164035797119141},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4914284944534302},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.47174322605133057},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.4620238244533539},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.4573712646961212},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.447786420583725},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4214667081832886},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36411046981811523},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.35678431391716003},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3072059750556946},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.28201329708099365},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.26052284240722656},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24416884779930115},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1077432930469513},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0951763391494751},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.09464475512504578},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/latw.2016.7483353","is_oa":false,"landing_page_url":"https://doi.org/10.1109/latw.2016.7483353","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 17th Latin-American Test Symposium (LATS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.550000011920929,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1488372642","https://openalex.org/W1940169316","https://openalex.org/W2044330427","https://openalex.org/W2078179095","https://openalex.org/W2114301751","https://openalex.org/W2142637184","https://openalex.org/W2154665706","https://openalex.org/W2156294156","https://openalex.org/W2164012847","https://openalex.org/W2166006392","https://openalex.org/W2262295232","https://openalex.org/W2413518988","https://openalex.org/W3144234790","https://openalex.org/W6683054823","https://openalex.org/W6684511688"],"related_works":["https://openalex.org/W2117563988","https://openalex.org/W2120257283","https://openalex.org/W2132684947","https://openalex.org/W2165817266","https://openalex.org/W2157212570","https://openalex.org/W2093968635","https://openalex.org/W2543176856","https://openalex.org/W1493811107","https://openalex.org/W1910267371","https://openalex.org/W3088373974"],"abstract_inverted_index":{"This":[0],"work":[1],"presents":[2],"the":[3,12,26,41],"validation":[4],"in":[5,40,81],"silicon":[6],"of":[7,14,16,28,67],"a":[8,69],"test":[9,34,70],"chip":[10],"for":[11],"evaluation":[13],"ensembles":[15],"combinational":[17],"CMOS":[18],"gates":[19],"(cell":[20],"library).":[21],"The":[22,53,75],"design":[23,64],"methodology":[24],"and":[25,32,55,72,79],"architecture":[27],"this":[29,82],"simple,":[30],"efficient":[31],"easy-to-use":[33],"circuit":[35,71],"were":[36],"already":[37],"proposed":[38],"theoretically":[39],"past,":[42],"having":[43],"been":[44],"demonstrated":[45],"its":[46,73],"functionality":[47],"only":[48],"through":[49],"partial":[50],"electrical":[51],"simulations.":[52],"fabrication":[54],"measurements":[56],"over":[57],"on-silicon":[58],"prototype":[59],"provide":[60],"important":[61],"information":[62],"about":[63],"improvement":[65],"possibilities":[66],"such":[68],"architecture.":[74],"results":[76],"are":[77],"presented":[78],"discussed":[80],"paper.":[83]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}