{"id":"https://openalex.org/W1875253360","doi":"https://doi.org/10.1109/latw.2015.7102412","title":"A controllable setup and propagation delay flip-flop design","display_name":"A controllable setup and propagation delay flip-flop design","publication_year":2015,"publication_date":"2015-03-01","ids":{"openalex":"https://openalex.org/W1875253360","doi":"https://doi.org/10.1109/latw.2015.7102412","mag":"1875253360"},"language":"en","primary_location":{"id":"doi:10.1109/latw.2015.7102412","is_oa":false,"landing_page_url":"https://doi.org/10.1109/latw.2015.7102412","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 16th Latin-American Test Symposium (LATS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000511492","display_name":"Alexandro Giron-Allende","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Alexandro Giron-Allende","raw_affiliation_strings":["Freescale Semiconductor, Guadalajara, Mexico","Freescale Semiconductor, Guadalajara, Mexico#TAB#"],"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor, Guadalajara, Mexico","institution_ids":[]},{"raw_affiliation_string":"Freescale Semiconductor, Guadalajara, Mexico#TAB#","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049780346","display_name":"Victor Avenda\u00f1o","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Victor Avendano","raw_affiliation_strings":["Freescale Semiconductor, Guadalajara, Mexico","Freescale Semiconductor, Guadalajara, Mexico#TAB#"],"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor, Guadalajara, Mexico","institution_ids":[]},{"raw_affiliation_string":"Freescale Semiconductor, Guadalajara, Mexico#TAB#","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109661490","display_name":"Esteban Mart\u00ednez-Guerrero","orcid":null},"institutions":[{"id":"https://openalex.org/I113686770","display_name":"Instituto Tecnol\u00f3gico y de Estudios Superiores de Occidente","ror":"https://ror.org/00cwp6m07","country_code":"MX","type":"education","lineage":["https://openalex.org/I113686770"]},{"id":"https://openalex.org/I193181351","display_name":"Universidad de Guadalajara","ror":"https://ror.org/043xj7k26","country_code":"MX","type":"education","lineage":["https://openalex.org/I193181351"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"Esteban Martinez-Guerrero","raw_affiliation_strings":["Department of Electronics Systems and Informatics, ITESO-The Jesuit University of Guadalajara, Guadalajara, Mexico","ITESO-The Jesuit University of Guadalajara, Guadalajara, 45604, Mexico"],"affiliations":[{"raw_affiliation_string":"Department of Electronics Systems and Informatics, ITESO-The Jesuit University of Guadalajara, Guadalajara, Mexico","institution_ids":["https://openalex.org/I113686770","https://openalex.org/I193181351"]},{"raw_affiliation_string":"ITESO-The Jesuit University of Guadalajara, Guadalajara, 45604, Mexico","institution_ids":["https://openalex.org/I193181351"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5000511492"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.04555087,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/flip-flop","display_name":"Flip-flop","score":0.9411188364028931},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.6947057247161865},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6573343873023987},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6082416772842407},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5403419137001038},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4928567409515381},{"id":"https://openalex.org/keywords/margin","display_name":"Margin (machine learning)","score":0.43903228640556335},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19510751962661743},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.1089404821395874},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.09163802862167358}],"concepts":[{"id":"https://openalex.org/C2781007278","wikidata":"https://www.wikidata.org/wiki/Q183406","display_name":"Flip-flop","level":3,"score":0.9411188364028931},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.6947057247161865},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6573343873023987},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6082416772842407},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5403419137001038},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4928567409515381},{"id":"https://openalex.org/C774472","wikidata":"https://www.wikidata.org/wiki/Q6760393","display_name":"Margin (machine learning)","level":2,"score":0.43903228640556335},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19510751962661743},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.1089404821395874},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.09163802862167358},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/latw.2015.7102412","is_oa":false,"landing_page_url":"https://doi.org/10.1109/latw.2015.7102412","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 16th Latin-American Test Symposium (LATS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1971528709","https://openalex.org/W2027647144","https://openalex.org/W2063862000","https://openalex.org/W2066597322","https://openalex.org/W2069217703","https://openalex.org/W2086447087","https://openalex.org/W2100332326","https://openalex.org/W2109195618","https://openalex.org/W2113735631","https://openalex.org/W2122502313","https://openalex.org/W2127639550","https://openalex.org/W2141881829","https://openalex.org/W2156640922","https://openalex.org/W4237249613","https://openalex.org/W6819126557"],"related_works":["https://openalex.org/W2109445684","https://openalex.org/W2572576974","https://openalex.org/W1875253360","https://openalex.org/W3008786049","https://openalex.org/W98453623","https://openalex.org/W2039177842","https://openalex.org/W2136396860","https://openalex.org/W2139145693","https://openalex.org/W2171186885","https://openalex.org/W2081082331"],"abstract_inverted_index":{"A":[0],"Controllable":[1],"flip":[2],"flop":[3],"design":[4],"for":[5],"sequential":[6],"synchronous":[7],"systems":[8],"is":[9,18,35,49,56,86],"proposed.":[10],"The":[11,83],"flip-flop":[12,59,76,85],"setup":[13,23,60],"time":[14,24,61],"and":[15,25,62,68,88],"propagation":[16,64],"delay":[17,26,65],"controlled":[19],"with":[20],"an":[21],"additional":[22],"control":[27,72],"(SDC)":[28],"input.":[29],"With":[30],"this":[31,46],"SDC":[32,54,71],"enable,":[33],"it":[34,48],"possible":[36],"to":[37],"enhance":[38],"the":[39,53,58,70,75],"circuit":[40],"timing":[41,79],"performance":[42],"when":[43,52,69],"required.":[44],"In":[45],"paper,":[47],"shown":[50],"that":[51],"input":[55],"enabled,":[57],"Clk-Q":[63],"are":[66],"reduced,":[67],"remains":[73],"disabled,":[74],"reduces":[77],"its":[78],"margin":[80],"saving":[81],"power.":[82],"proposed":[84],"designed":[87],"characterized":[89],"in":[90],"a":[91],"TSMC":[92],"28":[93],"nm":[94],"bulk":[95],"CMOS":[96],"technology.":[97]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
