{"id":"https://openalex.org/W2007131406","doi":"https://doi.org/10.1109/latw.2011.5985927","title":"Modeling the effect of process variations on the timing response of nanometer digital circuits","display_name":"Modeling the effect of process variations on the timing response of nanometer digital circuits","publication_year":2011,"publication_date":"2011-03-01","ids":{"openalex":"https://openalex.org/W2007131406","doi":"https://doi.org/10.1109/latw.2011.5985927","mag":"2007131406"},"language":"en","primary_location":{"id":"doi:10.1109/latw.2011.5985927","is_oa":false,"landing_page_url":"https://doi.org/10.1109/latw.2011.5985927","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 12th Latin American Test Workshop (LATW)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014518141","display_name":"J. Freijedo","orcid":"https://orcid.org/0000-0002-5462-173X"},"institutions":[{"id":"https://openalex.org/I6289922","display_name":"Universidade de Vigo","ror":"https://ror.org/05rdf8595","country_code":"ES","type":"education","lineage":["https://openalex.org/I6289922"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"J. Freijedo","raw_affiliation_strings":["University of Vigo, Spain","University of Vigo, Spain,"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Vigo, Spain","institution_ids":["https://openalex.org/I6289922"]},{"raw_affiliation_string":"University of Vigo, Spain,","institution_ids":["https://openalex.org/I6289922"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018531470","display_name":"J. Semi\u00e3o","orcid":"https://orcid.org/0000-0002-7667-7910"},"institutions":[{"id":"https://openalex.org/I71503853","display_name":"University of Algarve","ror":"https://ror.org/014g34x36","country_code":"PT","type":"education","lineage":["https://openalex.org/I71503853"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"J. Semi\u00e3o","raw_affiliation_strings":["University of Algarve Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Algarve Portugal","institution_ids":["https://openalex.org/I71503853"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057597956","display_name":"Juan J. Rodr\u00edguez-Andina","orcid":"https://orcid.org/0000-0002-0919-1793"},"institutions":[{"id":"https://openalex.org/I6289922","display_name":"Universidade de Vigo","ror":"https://ror.org/05rdf8595","country_code":"ES","type":"education","lineage":["https://openalex.org/I6289922"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"J. J. Rodr\u00edguez-Andina","raw_affiliation_strings":["University of Vigo, Spain","University of Vigo, Spain,"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Vigo, Spain","institution_ids":["https://openalex.org/I6289922"]},{"raw_affiliation_string":"University of Vigo, Spain,","institution_ids":["https://openalex.org/I6289922"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056273734","display_name":"Fabian Vargas","orcid":"https://orcid.org/0000-0002-3871-6464"},"institutions":[{"id":"https://openalex.org/I45643870","display_name":"Pontif\u00edcia Universidade Cat\u00f3lica do Rio Grande do Sul","ror":"https://ror.org/025vmq686","country_code":"BR","type":"education","lineage":["https://openalex.org/I45643870"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"F. Vargas","raw_affiliation_strings":["PUCRS, Brazil","PUCRS, Brazil#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"PUCRS, Brazil","institution_ids":["https://openalex.org/I45643870"]},{"raw_affiliation_string":"PUCRS, Brazil#TAB#","institution_ids":["https://openalex.org/I45643870"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039557784","display_name":"I.C. Teixeira","orcid":"https://orcid.org/0000-0002-2642-5619"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"I. C. Teixeira","raw_affiliation_strings":["IST/TUL, INESC-ID Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IST/TUL, INESC-ID Portugal","institution_ids":["https://openalex.org/I121345201"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5058862498","display_name":"J.P. Teixeira","orcid":"https://orcid.org/0000-0002-0379-6257"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"J. P. Teixeira","raw_affiliation_strings":["IST/TUL, INESC-ID Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IST/TUL, INESC-ID Portugal","institution_ids":["https://openalex.org/I121345201"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.7899302244186401},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.6901962161064148},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6655763387680054},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.6528576612472534},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6442189812660217},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6078702807426453},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5882679224014282},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.5559000372886658},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5067227482795715},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.4720747470855713},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4599510729312897},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.41130921244621277},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22944414615631104},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2058137059211731}],"concepts":[{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.7899302244186401},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.6901962161064148},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6655763387680054},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.6528576612472534},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6442189812660217},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6078702807426453},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5882679224014282},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.5559000372886658},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5067227482795715},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.4720747470855713},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4599510729312897},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.41130921244621277},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22944414615631104},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2058137059211731},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/latw.2011.5985927","is_oa":false,"landing_page_url":"https://doi.org/10.1109/latw.2011.5985927","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 12th Latin American Test Workshop (LATW)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1977055509","https://openalex.org/W1994210188","https://openalex.org/W2094813825","https://openalex.org/W2097819249","https://openalex.org/W2105407012","https://openalex.org/W2114834460","https://openalex.org/W2132816157","https://openalex.org/W2138724413","https://openalex.org/W2153299515","https://openalex.org/W2162547872","https://openalex.org/W2170918065","https://openalex.org/W3145643822","https://openalex.org/W3150466398","https://openalex.org/W6677055117","https://openalex.org/W6683598130"],"related_works":["https://openalex.org/W4229446324","https://openalex.org/W2158805860","https://openalex.org/W3151506308","https://openalex.org/W2110367374","https://openalex.org/W2160859600","https://openalex.org/W3092420867","https://openalex.org/W2115729972","https://openalex.org/W2042032654","https://openalex.org/W2158291854","https://openalex.org/W2123535323"],"abstract_inverted_index":{"The":[0,146],"implementation":[1],"of":[2,33,43,50,60,81,108,115,149,157,169],"complex,":[3],"high-performance":[4],"functionality":[5],"in":[6,64,112],"nano-CMOS":[7],"technologies":[8],"faces":[9],"significant":[10],"design":[11,97],"and":[12,23,98,133,173],"test":[13,99],"challenges":[14],"related":[15],"to":[16,20,39,86,118,136,140,143],"the":[17,31,41,47,72,78,96,106,113,122,127,150,155],"increased":[18],"susceptibility":[19],"process":[21,44,87,116,158],"variations":[22,45,117,159],"environmental":[24],"or":[25],"operation-dependent":[26],"disturbances.":[27],"This":[28,89],"paper":[29],"describes":[30],"application":[32],"semi-empirical":[34],"propagation":[35],"delay":[36,82,141],"variation":[37],"models":[38,73],"estimate":[40],"effect":[42,156],"on":[46,57,160],"timing":[48],"response":[49],"nanometer":[51],"digital":[52],"circuits.":[53],"Experimental":[54],"results":[55],"based":[56],"electrical":[58],"simulations":[59],"a":[61,109],"circuit":[62,111],"designed":[63],"65nm":[65],"CMOS":[66],"technology":[67],"are":[68],"presented":[69],"demonstrating":[70],"that":[71,154],"can":[74,91,163],"be":[75,92,119,144,164],"used":[76,93],"for":[77],"analytical":[79],"derivation":[80],"variability":[83],"windows":[84,132],"associated":[85,135],"variations.":[88,175],"information":[90],"during":[94],"both":[95],"processes.":[100],"On":[101,121],"one":[102],"hand,":[103,124],"it":[104,125],"allows":[105,126],"robustness":[107],"given":[110],"presence":[114],"evaluated.":[120],"other":[123],"boundaries":[128],"between":[129],"expected":[130],"functional":[131],"those":[134,168],"abnormal":[137],"behaviors":[138],"due":[139],"faults":[142],"defined.":[145],"main":[147],"advantage":[148],"proposed":[151],"approach":[152],"is":[153],"circuits'":[161],"performance":[162],"jointly":[165],"analyzed":[166],"with":[167],"power":[170],"supply":[171],"voltage":[172],"temperature":[174]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
