{"id":"https://openalex.org/W2151814752","doi":"https://doi.org/10.1109/latw.2009.4813800","title":"Analog test bus architecture for small die size and limited pin count devices with internal IPs testability emphasis","display_name":"Analog test bus architecture for small die size and limited pin count devices with internal IPs testability emphasis","publication_year":2009,"publication_date":"2009-03-01","ids":{"openalex":"https://openalex.org/W2151814752","doi":"https://doi.org/10.1109/latw.2009.4813800","mag":"2151814752"},"language":"en","primary_location":{"id":"doi:10.1109/latw.2009.4813800","is_oa":false,"landing_page_url":"https://doi.org/10.1109/latw.2009.4813800","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 10th Latin American Test Workshop","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020721781","display_name":"E. R. da Silva","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"E. R. da Silva","raw_affiliation_strings":["Freescale Semiconductor, Inc., USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor, Inc., USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003238039","display_name":"Fl\u00e1vio B. Costa","orcid":"https://orcid.org/0000-0002-7554-1480"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"F. Costa","raw_affiliation_strings":["Freescale Semiconductor, Inc., USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor, Inc., USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006229352","display_name":"Frank Herman Behrens","orcid":"https://orcid.org/0000-0002-0273-1953"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"F. H. Behrens","raw_affiliation_strings":["Freescale Semiconductor, Inc., USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor, Inc., USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066151579","display_name":"R. S. Kickhofel","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"R. S. Kickhofel","raw_affiliation_strings":["Freescale Semiconductor, Inc., USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor, Inc., USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5018567929","display_name":"Ricardo Maltione","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"R. Maltione","raw_affiliation_strings":["Freescale Semiconductor, Inc., USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor, Inc., USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2681,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.61175246,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"1","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13293","display_name":"Engineering and Test Systems","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.7997557520866394},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.6555130481719971},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.6372517347335815},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6244769096374512},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5911144018173218},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.5616668462753296},{"id":"https://openalex.org/keywords/die","display_name":"Die (integrated circuit)","score":0.5240378975868225},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.5029975771903992},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.4714309275150299},{"id":"https://openalex.org/keywords/gate-count","display_name":"Gate count","score":0.4301457107067108},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.34977975487709045},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.34570667147636414},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3143049478530884},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.2508896589279175},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.08336290717124939}],"concepts":[{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.7997557520866394},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.6555130481719971},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.6372517347335815},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6244769096374512},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5911144018173218},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.5616668462753296},{"id":"https://openalex.org/C111106434","wikidata":"https://www.wikidata.org/wiki/Q1072430","display_name":"Die (integrated circuit)","level":2,"score":0.5240378975868225},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.5029975771903992},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.4714309275150299},{"id":"https://openalex.org/C2777892113","wikidata":"https://www.wikidata.org/wiki/Q5527005","display_name":"Gate count","level":2,"score":0.4301457107067108},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.34977975487709045},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.34570667147636414},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3143049478530884},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.2508896589279175},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08336290717124939},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/latw.2009.4813800","is_oa":false,"landing_page_url":"https://doi.org/10.1109/latw.2009.4813800","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 10th Latin American Test Workshop","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.5}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W2009655452","https://openalex.org/W2107178406","https://openalex.org/W2107657165","https://openalex.org/W2116839118","https://openalex.org/W2126019929","https://openalex.org/W2126513855","https://openalex.org/W2131610230","https://openalex.org/W2133208931","https://openalex.org/W2135331669","https://openalex.org/W2147105328","https://openalex.org/W2151780421","https://openalex.org/W2163739362","https://openalex.org/W2167896761","https://openalex.org/W4242038055"],"related_works":["https://openalex.org/W2107525390","https://openalex.org/W2157191248","https://openalex.org/W2118869825","https://openalex.org/W2150046587","https://openalex.org/W2142405811","https://openalex.org/W2114980936","https://openalex.org/W1925788181","https://openalex.org/W4245595174","https://openalex.org/W2115513740","https://openalex.org/W2539511314"],"abstract_inverted_index":{"The":[0],"crescent":[1],"complexity":[2,95],"of":[3,62,129],"Mixed":[4],"Signal":[5],"Integrated":[6],"Circuits":[7],"designed":[8],"for":[9,32,91],"small":[10,82,92],"die":[11,83],"size":[12,84],"and":[13,36,67,93,102,121,125],"limited":[14],"pin":[15,68],"count":[16],"applications":[17],"in":[18,58,71,111,132],"key":[19],"areas":[20],"such":[21],"as":[22],"embedded":[23],"applications,":[24],"introduces":[25],"a":[26,79,112,145],"challenge":[27],"on":[28,45],"the":[29,46,53,104,133,141],"IC":[30],"testability,":[31],"debug,":[33],"production":[34],"test":[35,42,64,73,105,114],"field":[37],"issue":[38],"control.":[39],"Traditional":[40],"analog":[41,142],"approaches":[43],"based":[44],"existing":[47],"standards":[48],"do":[49],"not":[50],"completely":[51],"address":[52],"problem":[54],"due":[55],"to":[56],"constraints":[57],"architecture":[59,108],"complexity,":[60],"need":[61],"dedicated":[63],"control":[65],"interfaces":[66],"limitations,":[69],"resulting":[70],"expressive":[72],"cost":[74,80],"impact.":[75],"This":[76,107],"work":[77],"discuss":[78],"effective,":[81],"area":[85],"Analog":[86],"Test":[87],"Bus":[88],"Interface":[89],"implemented":[90,110],"medium":[94],"ICs":[96],"improving":[97],"its":[98],"mixed":[99],"mode":[100],"interface":[101],"reducing":[103],"time.":[106],"was":[109,135],"silicon":[113],"vehicle,":[115],"0.25u":[116],"BiCMOS":[117],"technology,":[118],"where":[119],"measurements":[120],"results":[122],"are":[123],"presented":[124],"discussed.":[126],"An":[127],"improvement":[128],"around":[130],"70%":[131],"testability":[134],"obtained":[136],"with":[137],"this":[138],"approach,":[139],"regarding":[140],"blocks,":[143],"allowing":[144],"powerful":[146],"real":[147],"time":[148],"debug":[149],"channel.":[150]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}