{"id":"https://openalex.org/W2159679627","doi":"https://doi.org/10.1109/latw.2009.4813795","title":"NBTI-aware technique for transistor sizing of high-performance CMOS gates","display_name":"NBTI-aware technique for transistor sizing of high-performance CMOS gates","publication_year":2009,"publication_date":"2009-03-01","ids":{"openalex":"https://openalex.org/W2159679627","doi":"https://doi.org/10.1109/latw.2009.4813795","mag":"2159679627"},"language":"en","primary_location":{"id":"doi:10.1109/latw.2009.4813795","is_oa":false,"landing_page_url":"https://doi.org/10.1109/latw.2009.4813795","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 10th Latin American Test Workshop","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5003461144","display_name":"Maur\u00edcio Banaszeski da Silva","orcid":"https://orcid.org/0000-0001-7434-6432"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Mauricio B. da Silva","raw_affiliation_strings":["Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010001207","display_name":"Vin\u00edcius Valduga de Almeida Camargo","orcid":"https://orcid.org/0000-0003-2006-3642"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Vinicius V. A. Camargo","raw_affiliation_strings":["Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009474826","display_name":"Lucas Brusamarello","orcid":null},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Lucas Brusamarello","raw_affiliation_strings":["Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022015482","display_name":"Gilson Wirth","orcid":"https://orcid.org/0000-0002-4990-5113"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Gilson I. Wirth","raw_affiliation_strings":["Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5042832490","display_name":"Roberto da Silva","orcid":"https://orcid.org/0000-0001-6110-0441"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Roberto da Silva","raw_affiliation_strings":["Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I130442723"],"apc_list":null,"apc_paid":null,"fwci":1.4563,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.81820311,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.8498636484146118},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.8080315589904785},{"id":"https://openalex.org/keywords/inverter","display_name":"Inverter","score":0.7463089227676392},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.710109293460846},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.6820865273475647},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.619947075843811},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6050800681114197},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5640642642974854},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.5337952375411987},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.47316938638687134},{"id":"https://openalex.org/keywords/nor-gate","display_name":"NOR gate","score":0.4690592288970947},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.4690573513507843},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.46520644426345825},{"id":"https://openalex.org/keywords/nand-logic","display_name":"NAND logic","score":0.46059903502464294},{"id":"https://openalex.org/keywords/gate-equivalent","display_name":"Gate equivalent","score":0.4604945480823517},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.44073486328125},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3327140808105469},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.30834561586380005},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.23923617601394653},{"id":"https://openalex.org/keywords/gate-oxide","display_name":"Gate oxide","score":0.13213565945625305},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.08621034026145935},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.05528697371482849}],"concepts":[{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.8498636484146118},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.8080315589904785},{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.7463089227676392},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.710109293460846},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.6820865273475647},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.619947075843811},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6050800681114197},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5640642642974854},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.5337952375411987},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.47316938638687134},{"id":"https://openalex.org/C126445297","wikidata":"https://www.wikidata.org/wiki/Q8065380","display_name":"NOR gate","level":4,"score":0.4690592288970947},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.4690573513507843},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.46520644426345825},{"id":"https://openalex.org/C7234692","wikidata":"https://www.wikidata.org/wiki/Q4116068","display_name":"NAND logic","level":4,"score":0.46059903502464294},{"id":"https://openalex.org/C60697091","wikidata":"https://www.wikidata.org/wiki/Q5527009","display_name":"Gate equivalent","level":5,"score":0.4604945480823517},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.44073486328125},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3327140808105469},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.30834561586380005},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.23923617601394653},{"id":"https://openalex.org/C2361726","wikidata":"https://www.wikidata.org/wiki/Q5527031","display_name":"Gate oxide","level":4,"score":0.13213565945625305},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.08621034026145935},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.05528697371482849},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/latw.2009.4813795","is_oa":false,"landing_page_url":"https://doi.org/10.1109/latw.2009.4813795","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 10th Latin American Test Workshop","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5400000214576721,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W2101686625","https://openalex.org/W2120893974","https://openalex.org/W2122757690","https://openalex.org/W2127877371","https://openalex.org/W2142047886","https://openalex.org/W2143901474","https://openalex.org/W4229927883","https://openalex.org/W4247815215"],"related_works":["https://openalex.org/W188762367","https://openalex.org/W2565020286","https://openalex.org/W4361799621","https://openalex.org/W1017999001","https://openalex.org/W4295177619","https://openalex.org/W2109857948","https://openalex.org/W1987908008","https://openalex.org/W1789158442","https://openalex.org/W2791832526","https://openalex.org/W2886135960"],"abstract_inverted_index":{"NBTI":[0,12],"imposes":[1],"a":[2,34,59,74,84,89],"challenge":[3],"for":[4,39],"the":[5,18,45,80],"design":[6],"of":[7,15,17,26,54],"circuits":[8,28],"in":[9],"DSM":[10],"technologies.":[11],"causes":[13],"increase":[14],"Vt":[16],"PMOS":[19],"transistors,":[20],"thus":[21],"leading":[22],"to":[23,73,93,102],"timing":[24],"degradation":[25],"CMOS":[27,41,104],"over":[29],"time.":[30],"This":[31],"manuscript":[32],"presents":[33,65],"NBTI-aware":[35],"transistor":[36],"sizing":[37,76],"technique":[38],"high-performance":[40],"gates,":[42,106],"which":[43],"improves":[44],"cell":[46],"reliability":[47],"with":[48],"minimum":[49],"area":[50],"penalty.":[51],"The":[52,95],"delay":[53,67,90],"an":[55],"inverter":[56],"designed":[57],"on":[58],"32nm":[60],"technology":[61],"using":[62,79],"our":[63],"methodology":[64,96],"6%":[66],"reduction":[68],"at":[69],"year":[70],"3":[71],"compared":[72],"traditional":[75],"methodology,":[77],"both":[78],"same":[81],"area.":[82],"For":[83],"NAND":[85],"gate":[86],"we":[87],"achieved":[88],"improvement":[91],"up":[92],"11%.":[94],"here":[97],"proposed":[98],"can":[99],"be":[100],"extended":[101],"other":[103],"logic":[105],"including":[107],"complex":[108],"gates.":[109]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}