{"id":"https://openalex.org/W4381730549","doi":"https://doi.org/10.1109/lats58125.2023.10154486","title":"Low cost external serial interface watchdog for SoCs and FPGAs automatic characterization tests","display_name":"Low cost external serial interface watchdog for SoCs and FPGAs automatic characterization tests","publication_year":2023,"publication_date":"2023-03-21","ids":{"openalex":"https://openalex.org/W4381730549","doi":"https://doi.org/10.1109/lats58125.2023.10154486"},"language":"en","primary_location":{"id":"doi:10.1109/lats58125.2023.10154486","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/lats58125.2023.10154486","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE 24th Latin American Test Symposium (LATS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049430681","display_name":"Paolo Bernardi","orcid":"https://orcid.org/0000-0002-0985-9327"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Paolo Bernardi","raw_affiliation_strings":["Politecnico di Torino,Italy","Politecnico di Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Torino,Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Politecnico di Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080934364","display_name":"Gabriele Filipponi","orcid":"https://orcid.org/0000-0002-1436-3764"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Gabriele Filipponi","raw_affiliation_strings":["Politecnico di Torino,Italy","Politecnico di Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Torino,Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Politecnico di Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031839947","display_name":"Tommaso Foscale","orcid":"https://orcid.org/0009-0000-0735-087X"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Tommaso Foscale","raw_affiliation_strings":["Politecnico di Torino,Italy","Politecnico di Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Torino,Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Politecnico di Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5041202522","display_name":"Giorgio Insinga","orcid":"https://orcid.org/0000-0001-6316-4123"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Giorgio Insinga","raw_affiliation_strings":["Politecnico di Torino,Italy","Politecnico di Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Torino,Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Politecnico di Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5049430681"],"corresponding_institution_ids":["https://openalex.org/I177477856"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.07302136,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12495","display_name":"Electrostatic Discharge in Electronics","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reset","display_name":"Reset (finance)","score":0.7346502542495728},{"id":"https://openalex.org/keywords/laptop","display_name":"Laptop","score":0.6987879276275635},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6949402689933777},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6733934879302979},{"id":"https://openalex.org/keywords/device-under-test","display_name":"Device under test","score":0.6276668310165405},{"id":"https://openalex.org/keywords/serial-communication","display_name":"Serial communication","score":0.5629479289054871},{"id":"https://openalex.org/keywords/serial-port","display_name":"Serial port","score":0.5153400301933289},{"id":"https://openalex.org/keywords/automatic-test-equipment","display_name":"Automatic test equipment","score":0.5098944902420044},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.5091838240623474},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5014932155609131},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4899543821811676},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.47117048501968384},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.4647815227508545},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4371534585952759},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.35112637281417847},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.32052069902420044},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.15109139680862427},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10470789670944214}],"concepts":[{"id":"https://openalex.org/C2779795794","wikidata":"https://www.wikidata.org/wiki/Q7315343","display_name":"Reset (finance)","level":2,"score":0.7346502542495728},{"id":"https://openalex.org/C2780008327","wikidata":"https://www.wikidata.org/wiki/Q3962","display_name":"Laptop","level":2,"score":0.6987879276275635},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6949402689933777},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6733934879302979},{"id":"https://openalex.org/C76249512","wikidata":"https://www.wikidata.org/wiki/Q1206780","display_name":"Device under test","level":3,"score":0.6276668310165405},{"id":"https://openalex.org/C51707140","wikidata":"https://www.wikidata.org/wiki/Q518280","display_name":"Serial communication","level":2,"score":0.5629479289054871},{"id":"https://openalex.org/C102349902","wikidata":"https://www.wikidata.org/wiki/Q385390","display_name":"Serial port","level":3,"score":0.5153400301933289},{"id":"https://openalex.org/C141842801","wikidata":"https://www.wikidata.org/wiki/Q363815","display_name":"Automatic test equipment","level":3,"score":0.5098944902420044},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.5091838240623474},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5014932155609131},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4899543821811676},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.47117048501968384},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.4647815227508545},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4371534585952759},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.35112637281417847},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.32052069902420044},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.15109139680862427},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10470789670944214},{"id":"https://openalex.org/C195266298","wikidata":"https://www.wikidata.org/wiki/Q2165620","display_name":"Scattering parameters","level":2,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C106159729","wikidata":"https://www.wikidata.org/wiki/Q2294553","display_name":"Financial economics","level":1,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/lats58125.2023.10154486","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/lats58125.2023.10154486","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE 24th Latin American Test Symposium (LATS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2365780630","https://openalex.org/W2354040300","https://openalex.org/W2369521450","https://openalex.org/W2071855843","https://openalex.org/W2767749057","https://openalex.org/W2349653672","https://openalex.org/W2348306694","https://openalex.org/W2392908833","https://openalex.org/W2373915683","https://openalex.org/W2373343798"],"abstract_inverted_index":{"Manufacturers":[0],"must":[1],"characterize":[2],"their":[3],"design":[4],"deeply":[5],"when":[6],"designing":[7],"and":[8,13,19,54,59,66,83,108,130,132,177],"producing":[9],"devices":[10,50],"like":[11],"FPGAs":[12,55],"SoCs.":[14],"Information":[15],"collected":[16],"through":[17,98,180],"simulation":[18],"physical":[20],"experiments":[21],"is":[22,116],"the":[23,33,73,77,85,89,92,96,104,134,165,169,172,175],"primary":[24],"data":[25],"source":[26],"for":[27,119],"manufacturers":[28],"that":[29,122],"can":[30,68,163],"then":[31],"decide":[32],"optimal":[34],"working":[35],"ranges":[36],"of":[37,64,128,185],"multiple":[38],"critical":[39],"parameters":[40,75,94],"such":[41,51],"as":[42,52],"operating":[43],"voltage,":[44],"frequency,":[45],"temperatures,":[46],"etc.":[47],"With":[48],"complex":[49],"SoCs,":[53],"with":[56],"integrated":[57],"PLLs":[58],"voltage":[60,65],"regulators,":[61],"each":[62],"combination":[63],"frequency":[67],"be":[69,138],"checked":[70],"by":[71],"communicating":[72],"desired":[74,93],"to":[76,95,110],"DUT,":[78,176],"running":[79],"a":[80,125,139],"functional":[81],"test,":[82],"observing":[84],"results.":[86],"However":[87],"once":[88],"ATE":[90,135],"sends":[91],"DUT":[97,105,145],"SPI":[99],"or":[100],"other":[101],"serial":[102,153],"interfaces,":[103],"may":[106,123,136],"freeze":[107],"stop":[109],"accept":[111],"new":[112],"commands":[113],"entirely.":[114],"This":[115,148],"particularly":[117],"problematic":[118],"targeted":[120],"characterization":[121],"include":[124],"minimal":[126],"number":[127],"boards":[129],"DUTs":[131],"where":[133],"simply":[137],"simple":[140],"laptop":[141],"without":[142],"any":[143],"automatic":[144],"reset":[146],"capabilities.":[147],"paper":[149],"presents":[150],"an":[151,158],"external":[152],"communication":[154],"watchdog":[155,162],"designed":[156],"using":[157],"ESP32-based":[159],"board.":[160],"Our":[161],"detect":[164],"communications":[166],"coming":[167],"from":[168,174],"ATE,":[170],"monitor":[171],"answers":[173],"restart":[178],"it":[179],"power":[181],"cycling":[182],"in":[183],"case":[184],"freezing.":[186]},"counts_by_year":[],"updated_date":"2025-12-24T23:09:58.560324","created_date":"2025-10-10T00:00:00"}
