{"id":"https://openalex.org/W7147356263","doi":"https://doi.org/10.1109/lascas67804.2026.11457166","title":"Evolutionary Optimization for Low-Voltage, Wide-Temperature Range SRAM Cell Designs","display_name":"Evolutionary Optimization for Low-Voltage, Wide-Temperature Range SRAM Cell Designs","publication_year":2026,"publication_date":"2026-02-24","ids":{"openalex":"https://openalex.org/W7147356263","doi":"https://doi.org/10.1109/lascas67804.2026.11457166"},"language":null,"primary_location":{"id":"doi:10.1109/lascas67804.2026.11457166","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lascas67804.2026.11457166","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE 17th Latin America Symposium on Circuits and System (LASCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5132578071","display_name":"Rafael Knust","orcid":null},"institutions":[{"id":"https://openalex.org/I122140584","display_name":"Universidade Federal do Rio de Janeiro","ror":"https://ror.org/03490as77","country_code":"BR","type":"education","lineage":["https://openalex.org/I122140584"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"Rafael Knust","raw_affiliation_strings":["Centro Federal de Educa&#x00E7;&#x00E3;o Tecnol&#x00F3;gica do Rio de Janeiro (CEFET/RJ),Rio de Janeiro,RJ,Brazil"],"affiliations":[{"raw_affiliation_string":"Centro Federal de Educa&#x00E7;&#x00E3;o Tecnol&#x00F3;gica do Rio de Janeiro (CEFET/RJ),Rio de Janeiro,RJ,Brazil","institution_ids":["https://openalex.org/I122140584"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112591822","display_name":"Thiago Brito","orcid":null},"institutions":[{"id":"https://openalex.org/I62885914","display_name":"Universidade Federal do Amazonas","ror":"https://ror.org/02263ky35","country_code":"BR","type":"education","lineage":["https://openalex.org/I62885914"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Thiago Brito","raw_affiliation_strings":["Universidade Federal do Amazonas (UFAM),Manaus,AM,Brazil"],"affiliations":[{"raw_affiliation_string":"Universidade Federal do Amazonas (UFAM),Manaus,AM,Brazil","institution_ids":["https://openalex.org/I62885914"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075936421","display_name":"F. O. Oliveira","orcid":null},"institutions":[{"id":"https://openalex.org/I122140584","display_name":"Universidade Federal do Rio de Janeiro","ror":"https://ror.org/03490as77","country_code":"BR","type":"education","lineage":["https://openalex.org/I122140584"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Fernanda D.V.R. Oliveira","raw_affiliation_strings":["Universidade Federal do Rio de Janeiro (UFRJ),Rio de Janeiro,RJ,Brazil"],"affiliations":[{"raw_affiliation_string":"Universidade Federal do Rio de Janeiro (UFRJ),Rio de Janeiro,RJ,Brazil","institution_ids":["https://openalex.org/I122140584"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5022821090","display_name":"Fabi\u00e1n Olivera","orcid":"https://orcid.org/0000-0002-8120-2338"},"institutions":[{"id":"https://openalex.org/I122140584","display_name":"Universidade Federal do Rio de Janeiro","ror":"https://ror.org/03490as77","country_code":"BR","type":"education","lineage":["https://openalex.org/I122140584"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Fabi\u00e1n Olivera","raw_affiliation_strings":["Universidade Federal do Rio de Janeiro (UFRJ),Rio de Janeiro,RJ,Brazil"],"affiliations":[{"raw_affiliation_string":"Universidade Federal do Rio de Janeiro (UFRJ),Rio de Janeiro,RJ,Brazil","institution_ids":["https://openalex.org/I122140584"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5132578071"],"corresponding_institution_ids":["https://openalex.org/I122140584"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.92312291,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.7124999761581421,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.7124999761581421,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.1080000028014183,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.10350000113248825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.8773000240325928},{"id":"https://openalex.org/keywords/monte-carlo-method","display_name":"Monte Carlo method","score":0.6959999799728394},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.6833999752998352},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5859000086784363},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4932999908924103},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.47380000352859497},{"id":"https://openalex.org/keywords/evolutionary-algorithm","display_name":"Evolutionary algorithm","score":0.4348999857902527},{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.4253999888896942}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.8773000240325928},{"id":"https://openalex.org/C19499675","wikidata":"https://www.wikidata.org/wiki/Q232207","display_name":"Monte Carlo method","level":2,"score":0.6959999799728394},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.6833999752998352},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5859000086784363},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4932999908924103},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.48339998722076416},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.47380000352859497},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4596000015735626},{"id":"https://openalex.org/C159149176","wikidata":"https://www.wikidata.org/wiki/Q14489129","display_name":"Evolutionary algorithm","level":2,"score":0.4348999857902527},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.4253999888896942},{"id":"https://openalex.org/C204323151","wikidata":"https://www.wikidata.org/wiki/Q905424","display_name":"Range (aeronautics)","level":2,"score":0.3912000060081482},{"id":"https://openalex.org/C112972136","wikidata":"https://www.wikidata.org/wiki/Q7595718","display_name":"Stability (learning theory)","level":2,"score":0.35530000925064087},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.34709998965263367},{"id":"https://openalex.org/C62064638","wikidata":"https://www.wikidata.org/wiki/Q553878","display_name":"Design for manufacturability","level":2,"score":0.3343999981880188},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.298799991607666},{"id":"https://openalex.org/C192615534","wikidata":"https://www.wikidata.org/wiki/Q7247268","display_name":"Process corners","level":3,"score":0.2897000014781952},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.2799000144004822},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2791000008583069},{"id":"https://openalex.org/C8880873","wikidata":"https://www.wikidata.org/wiki/Q187787","display_name":"Genetic algorithm","level":2,"score":0.2705000042915344},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.266400009393692},{"id":"https://openalex.org/C45786274","wikidata":"https://www.wikidata.org/wiki/Q3333611","display_name":"Kinetic Monte Carlo","level":3,"score":0.2630999982357025},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.2542000114917755},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.25360000133514404},{"id":"https://openalex.org/C34559072","wikidata":"https://www.wikidata.org/wiki/Q2334061","display_name":"Design of experiments","level":2,"score":0.2508000135421753}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/lascas67804.2026.11457166","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lascas67804.2026.11457166","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE 17th Latin America Symposium on Circuits and System (LASCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.47311100363731384,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1969711674","https://openalex.org/W2027945080","https://openalex.org/W2155153274","https://openalex.org/W2172203429","https://openalex.org/W2585329946","https://openalex.org/W2605939216","https://openalex.org/W2895208760","https://openalex.org/W2998324702","https://openalex.org/W3160469020","https://openalex.org/W4295037072","https://openalex.org/W4391924506","https://openalex.org/W4406258823","https://openalex.org/W4411551098","https://openalex.org/W4412801637","https://openalex.org/W4413319021"],"related_works":[],"abstract_inverted_index":{"Variability":[0],"in":[1,15,86,116],"nanometer":[2],"CMOS":[3,94],"manufacturing":[4,72],"processes,":[5],"wide":[6],"operating":[7],"temperature":[8,128],"ranges,":[9],"and":[10,35,90,112,142],"continuous":[11],"supply":[12,123],"voltage":[13,124],"scaling":[14],"low-power":[16],"applications":[17],"present":[18,42],"significant":[19],"challenges":[20],"for":[21,49],"static":[22],"random-access":[23],"memory":[24],"(SRAM)":[25],"designs,":[26],"as":[27],"they":[28],"substantially":[29],"degrade":[30],"the":[31,64,77,80,101,113],"stability":[32],"of":[33,79,100,125,145],"read":[34],"write":[36],"operations.":[37],"In":[38],"this":[39],"paper,":[40],"we":[41],"a":[43,117],"variability-aware":[44],"evolutionary":[45],"algorithm":[46],"(EA)-based":[47],"approach":[48],"low-voltage,":[50],"widetemperature":[51],"range":[52,129],"SRAM":[53,103,120],"cell":[54,114],"designs.":[55],"The":[56],"proposed":[57],"framework":[58],"integrates":[59],"Monte":[60,97],"Carlo":[61,98],"simulations":[62,99],"into":[63],"EA":[65],"fitness":[66],"evaluation":[67],"to":[68,136],"enhance":[69],"robustness":[70],"against":[71],"process":[73],"variations.":[74],"To":[75],"validate":[76],"effectiveness":[78],"methodology,":[81],"design":[82],"examples":[83],"are":[84,105],"implemented":[85],"IHP":[87],"130":[88],"nm":[89,93],"TSMC":[91],"65":[92],"technologies.":[95],"Extensive":[96],"resulting":[102],"cells":[104],"performed,":[106],"covering":[107],"both":[108],"traditional":[109],"performance":[110],"margins":[111],"operation":[115,143],"8":[118],"kb":[119],"macro,":[121],"using":[122],"0.6":[126],"V,":[127],"from":[130],"<tex":[131,137],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[132,138],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">$0{":[133],"}^{\\circ}":[134,140],"\\mathrm{C}$</tex>":[135,141],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">$80{":[139],"frequency":[144],"40":[146],"MHz.":[147]},"counts_by_year":[],"updated_date":"2026-04-02T13:53:19.096889","created_date":"2026-04-02T00:00:00"}
