{"id":"https://openalex.org/W7147193804","doi":"https://doi.org/10.1109/lascas67804.2026.11457144","title":"Current-Starved Inverter Cell Design Trade-Offs for Single Capacitively Coupled Ring VCOs","display_name":"Current-Starved Inverter Cell Design Trade-Offs for Single Capacitively Coupled Ring VCOs","publication_year":2026,"publication_date":"2026-02-24","ids":{"openalex":"https://openalex.org/W7147193804","doi":"https://doi.org/10.1109/lascas67804.2026.11457144"},"language":null,"primary_location":{"id":"doi:10.1109/lascas67804.2026.11457144","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lascas67804.2026.11457144","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE 17th Latin America Symposium on Circuits and System (LASCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5118664004","display_name":"Ilan Sabaj","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Ilan Sabaj","raw_affiliation_strings":["Instituto de Ingeniería Eléctrica, Universidad de la República,Montevideo,Uruguay"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto de Ingeniería Eléctrica, Universidad de la República,Montevideo,Uruguay","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5118664002","display_name":"Santiago Bernardez","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Santiago Bernardez","raw_affiliation_strings":["Instituto de Ingeniería Eléctrica, Universidad de la República,Montevideo,Uruguay"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto de Ingeniería Eléctrica, Universidad de la República,Montevideo,Uruguay","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5118664003","display_name":"Ignacio Valettute","orcid":null},"institutions":[{"id":"https://openalex.org/I4210090832","display_name":"Blackrock Microsystems (United States)","ror":"https://ror.org/00bvzmn76","country_code":"US","type":"company","lineage":["https://openalex.org/I4210090832"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ignacio Valettute","raw_affiliation_strings":["Allegro MicroSystems,Uruguay"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Allegro MicroSystems,Uruguay","institution_ids":["https://openalex.org/I4210090832"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5077921771","display_name":"Mariana Siniscalchi","orcid":"https://orcid.org/0000-0001-5445-8453"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Mariana Siniscalchi","raw_affiliation_strings":["Instituto de Ingeniería Eléctrica, Universidad de la República,Montevideo,Uruguay"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto de Ingeniería Eléctrica, Universidad de la República,Montevideo,Uruguay","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.26540263,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.474700003862381,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.474700003862381,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.20489999651908875,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.08089999854564667,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/inverter","display_name":"Inverter","score":0.7330999970436096},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5436999797821045},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.47620001435279846},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.4383000135421753},{"id":"https://openalex.org/keywords/asymmetry","display_name":"Asymmetry","score":0.4381999969482422},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.399399995803833},{"id":"https://openalex.org/keywords/voltage-controlled-oscillator","display_name":"Voltage-controlled oscillator","score":0.39239999651908875},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.382999986410141}],"concepts":[{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.7330999970436096},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5436999797821045},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.48019999265670776},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.47620001435279846},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4480000138282776},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.4383000135421753},{"id":"https://openalex.org/C38976095","wikidata":"https://www.wikidata.org/wiki/Q752641","display_name":"Asymmetry","level":2,"score":0.4381999969482422},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.41190001368522644},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.399399995803833},{"id":"https://openalex.org/C5291336","wikidata":"https://www.wikidata.org/wiki/Q852341","display_name":"Voltage-controlled oscillator","level":3,"score":0.39239999651908875},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.382999986410141},{"id":"https://openalex.org/C2780378348","wikidata":"https://www.wikidata.org/wiki/Q25351438","display_name":"Ring (chemistry)","level":2,"score":0.35359999537467957},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.3440000116825104},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.33739998936653137},{"id":"https://openalex.org/C2780980858","wikidata":"https://www.wikidata.org/wiki/Q110022","display_name":"Dual (grammatical number)","level":2,"score":0.33390000462532043},{"id":"https://openalex.org/C44280652","wikidata":"https://www.wikidata.org/wiki/Q104837","display_name":"Phase (matter)","level":2,"score":0.3172999918460846},{"id":"https://openalex.org/C2777042010","wikidata":"https://www.wikidata.org/wiki/Q324963","display_name":"Power inverter","level":4,"score":0.2849999964237213},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.2727000117301941},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.2718000113964081},{"id":"https://openalex.org/C146847952","wikidata":"https://www.wikidata.org/wiki/Q933121","display_name":"Colpitts oscillator","level":5,"score":0.26190000772476196},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.25949999690055847},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.2556000053882599},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.2533999979496002},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.25270000100135803}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/lascas67804.2026.11457144","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lascas67804.2026.11457144","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE 17th Latin America Symposium on Circuits and System (LASCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1979386126","https://openalex.org/W2002184627","https://openalex.org/W2078269407","https://openalex.org/W2109844495","https://openalex.org/W2126934213","https://openalex.org/W2135441328","https://openalex.org/W2146167262","https://openalex.org/W3090108660","https://openalex.org/W3134851968","https://openalex.org/W3181222543","https://openalex.org/W4399993806","https://openalex.org/W4400678968","https://openalex.org/W4411725048"],"related_works":[],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,13,52],"comparative":[4],"study":[5],"of":[6],"inverter":[7,25,126],"cell":[8,85,93],"topologies":[9],"for":[10,42,125],"use":[11],"in":[12,128],"single":[14],"capacitively":[15],"coupled":[16],"(SCC)":[17],"ring":[18],"VCO":[19,130],"targeting":[20],"multi-phase":[21],"RF":[22],"applications.":[23],"Three":[24],"cells":[26,46],"are":[27,47],"investigated:":[28],"nMOS-only":[29],"(N),":[30],"pMOS-only":[31],"(P),":[32],"and":[33,80,97,102,119],"complementary":[34],"nMOS-pMOS":[35],"(NP),":[36],"each":[37],"implemented":[38],"with":[39,106],"current-starved":[40],"control":[41],"frequency":[43,71],"tuning.":[44],"The":[45,83],"designed":[48],"in$28-\\text{nm}$FD-SOI":[49],"technology":[50],"under":[51],"common":[53],"parameterization,":[54],"ensuring":[55],"that":[56],"performance":[57],"differences":[58],"arise":[59],"from":[60],"intrinsic":[61,113],"architectural":[62],"properties":[63],"rather":[64],"than":[65],"transistor":[66],"sizing.":[67],"Simulation":[68],"results":[69,111],"compare":[70],"tuning":[72,89],"range,":[73,90],"power":[74,108],"consumption,":[75],"output":[76],"swing,":[77],"signal":[78,117],"symmetry":[79,96],"phase":[81],"noise.":[82],"N":[84],"achieves":[86],"the":[87,91],"widest":[88],"NP":[92],"offers":[94],"better":[95],"the$\\mathrm{P}$cell":[98],"shows":[99],"limited":[100],"swing":[101],"higher":[103],"asymmetry":[104],"but":[105],"lower":[107],"consumption.":[109],"These":[110],"reveal":[112],"trade-offs":[114],"between":[115],"efficiency,":[116],"integrity,":[118],"spectral":[120],"purity,":[121],"providing":[122],"practical":[123],"guidelines":[124],"selection":[127],"SCC":[129],"designs.":[131]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2026-04-02T00:00:00"}