{"id":"https://openalex.org/W7146958096","doi":"https://doi.org/10.1109/lascas67804.2026.11457113","title":"Validation of the NVDLA Architecture via AWS-Based FPGA Co-Simulation Using the Alexnet Model","display_name":"Validation of the NVDLA Architecture via AWS-Based FPGA Co-Simulation Using the Alexnet Model","publication_year":2026,"publication_date":"2026-02-24","ids":{"openalex":"https://openalex.org/W7146958096","doi":"https://doi.org/10.1109/lascas67804.2026.11457113"},"language":null,"primary_location":{"id":"doi:10.1109/lascas67804.2026.11457113","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lascas67804.2026.11457113","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE 17th Latin America Symposium on Circuits and System (LASCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5132654196","display_name":"David Freidenson Bejar","orcid":null},"institutions":[{"id":"https://openalex.org/I2801109035","display_name":"ARM (United Kingdom)","ror":"https://ror.org/04mmhzs81","country_code":"GB","type":"company","lineage":["https://openalex.org/I2801109035"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"David Freidenson Bejar","raw_affiliation_strings":["Arm Ltd.,Cambridge,United Kingdom"],"affiliations":[{"raw_affiliation_string":"Arm Ltd.,Cambridge,United Kingdom","institution_ids":["https://openalex.org/I2801109035"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5123773164","display_name":"Mario Raffo Jara","orcid":null},"institutions":[{"id":"https://openalex.org/I65285256","display_name":"Pontificia Universidad Cat\u00f3lica del Per\u00fa","ror":"https://ror.org/00013q465","country_code":"PE","type":"education","lineage":["https://openalex.org/I65285256"]}],"countries":["PE"],"is_corresponding":false,"raw_author_name":"Mario Raffo Jara","raw_affiliation_strings":["Pontifical Catholic University of Peru (PUCP),Research Group in Microelectronics (GuE),Lima,Peru"],"affiliations":[{"raw_affiliation_string":"Pontifical Catholic University of Peru (PUCP),Research Group in Microelectronics (GuE),Lima,Peru","institution_ids":["https://openalex.org/I65285256"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5047132700","display_name":"Ernesto Cristopher Villegas Castillo","orcid":"https://orcid.org/0009-0005-8586-512X"},"institutions":[{"id":"https://openalex.org/I4210089203","display_name":"Cadence Design Systems (Germany)","ror":"https://ror.org/00d9ep044","country_code":"DE","type":"company","lineage":["https://openalex.org/I4210089203","https://openalex.org/I66217453"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Ernesto Cristopher Villegas Castillo","raw_affiliation_strings":["Cadence Design Systems,Munich,Germany"],"affiliations":[{"raw_affiliation_string":"Cadence Design Systems,Munich,Germany","institution_ids":["https://openalex.org/I4210089203"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5132654196"],"corresponding_institution_ids":["https://openalex.org/I2801109035"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.93004843,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11689","display_name":"Adversarial Robustness in Machine Learning","score":0.39629998803138733,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11689","display_name":"Adversarial Robustness in Machine Learning","score":0.39629998803138733,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10036","display_name":"Advanced Neural Network Applications","score":0.15299999713897705,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.07509999722242355,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7307999730110168},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.6733999848365784},{"id":"https://openalex.org/keywords/convolutional-neural-network","display_name":"Convolutional neural network","score":0.6516000032424927},{"id":"https://openalex.org/keywords/inference","display_name":"Inference","score":0.5333999991416931},{"id":"https://openalex.org/keywords/deep-learning","display_name":"Deep learning","score":0.487199991941452},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.46399998664855957},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.38040000200271606},{"id":"https://openalex.org/keywords/arm-architecture","display_name":"ARM architecture","score":0.3431999981403351}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.828000009059906},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7307999730110168},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.6733999848365784},{"id":"https://openalex.org/C81363708","wikidata":"https://www.wikidata.org/wiki/Q17084460","display_name":"Convolutional neural network","level":2,"score":0.6516000032424927},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5602999925613403},{"id":"https://openalex.org/C2776214188","wikidata":"https://www.wikidata.org/wiki/Q408386","display_name":"Inference","level":2,"score":0.5333999991416931},{"id":"https://openalex.org/C108583219","wikidata":"https://www.wikidata.org/wiki/Q197536","display_name":"Deep learning","level":2,"score":0.487199991941452},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.46399998664855957},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.45980000495910645},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.4106999933719635},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.38040000200271606},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.37610000371932983},{"id":"https://openalex.org/C26771161","wikidata":"https://www.wikidata.org/wiki/Q16980","display_name":"ARM architecture","level":2,"score":0.3431999981403351},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.3131999969482422},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.30720001459121704},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.30379998683929443},{"id":"https://openalex.org/C25344961","wikidata":"https://www.wikidata.org/wiki/Q192726","display_name":"Virtual machine","level":2,"score":0.29330000281333923},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.2924000024795532},{"id":"https://openalex.org/C2780991453","wikidata":"https://www.wikidata.org/wiki/Q3408177","display_name":"Virtual prototyping","level":2,"score":0.27489998936653137},{"id":"https://openalex.org/C52622490","wikidata":"https://www.wikidata.org/wiki/Q1026626","display_name":"Feature extraction","level":2,"score":0.26499998569488525},{"id":"https://openalex.org/C34736171","wikidata":"https://www.wikidata.org/wiki/Q918333","display_name":"Preprocessor","level":2,"score":0.2646999955177307},{"id":"https://openalex.org/C74193536","wikidata":"https://www.wikidata.org/wiki/Q574844","display_name":"Kernel (algebra)","level":2,"score":0.25859999656677246},{"id":"https://openalex.org/C2778751112","wikidata":"https://www.wikidata.org/wiki/Q835016","display_name":"Window (computing)","level":2,"score":0.251800000667572},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2517000138759613}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/lascas67804.2026.11457113","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lascas67804.2026.11457113","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE 17th Latin America Symposium on Circuits and System (LASCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8913285136222839}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2155893237","https://openalex.org/W2194775991","https://openalex.org/W2486847405","https://openalex.org/W2563468918","https://openalex.org/W2799962670","https://openalex.org/W2908802621","https://openalex.org/W2999066514","https://openalex.org/W3131288814","https://openalex.org/W4212861581"],"related_works":[],"abstract_inverted_index":{"Deep":[0,25],"neural":[1,115],"network":[2],"(DNN)":[3],"inference":[4,110,123],"presents":[5],"growing":[6],"challenges":[7],"in":[8,125,151],"computational":[9],"complexity,":[10],"memory":[11],"bandwidth,":[12],"and":[13,74,107,140],"energy":[14],"efficiency.":[15],"To":[16],"address":[17],"these":[18],"demands,":[19],"this":[20],"work":[21],"validates":[22],"the":[23,47,57,60,94,105,112,132,136,142],"NVIDIA":[24],"Learning":[26],"Accelerator":[27],"(NVDLA)":[28],"using":[29],"a":[30,63,68],"hybrid":[31,137],"co-simulation":[32,146],"platform":[33,45,139],"deployed":[34],"on":[35,59],"Amazon":[36],"Web":[37],"Services":[38],"(AWS)":[39],"EC2":[40],"F1":[41],"FPGA":[42,61],"instances.":[43],"The":[44],"integrates":[46],"<tex":[48],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[49],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">$\\boldsymbol{n}":[50],"\\boldsymbol{v}":[51],"\\_\\boldsymbol{s}$</tex>":[52],"mall":[53],"RT-level":[54],"configuration":[55],"of":[56,93,111,135,144],"NVDLA":[58,138],"with":[62,121],"virtual":[64],"prototype":[65],"(VP)":[66],"comprising":[67],"QEMU-emulated":[69],"Arm":[70],"CPU,":[71],"SystemC/TLM-based":[72],"communication,":[73],"full":[75],"Linux":[76],"runtime":[77],"support.":[78],"Validation":[79],"was":[80],"conducted":[81],"through":[82],"three":[83],"stages:":[84],"(1)":[85],"hardware":[86],"regression":[87],"tests":[88,118],"to":[89,100],"ensure":[90],"block-level":[91],"correctness":[92],"NVDLA,":[95],"(2)":[96],"software":[97],"sanity":[98],"checks":[99],"verify":[101],"systemlevel":[102],"integration":[103],"within":[104],"VP,":[106],"(3)":[108],"end-to-end":[109],"AlexNet":[113,122],"convolutional":[114],"network.":[116],"All":[117],"passed":[119],"successfully,":[120],"completing":[124],"approximately":[126],"112":[127],"minutes.":[128],"These":[129],"results":[130],"confirm":[131],"functional":[133],"readiness":[134],"underscore":[141],"advantages":[143],"VP-FPGA":[145],"for":[147],"accelerating":[148],"hardware-software":[149],"codesign":[150],"deep":[152],"learning":[153],"accelerator":[154],"development.":[155]},"counts_by_year":[],"updated_date":"2026-04-02T13:53:19.096889","created_date":"2026-04-02T00:00:00"}