{"id":"https://openalex.org/W7147426314","doi":"https://doi.org/10.1109/lascas67804.2026.11457107","title":"Implementing a Dual RISC-V System-on-Chip Chiplet with Advanced Interface Bus","display_name":"Implementing a Dual RISC-V System-on-Chip Chiplet with Advanced Interface Bus","publication_year":2026,"publication_date":"2026-02-24","ids":{"openalex":"https://openalex.org/W7147426314","doi":"https://doi.org/10.1109/lascas67804.2026.11457107"},"language":null,"primary_location":{"id":"doi:10.1109/lascas67804.2026.11457107","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lascas67804.2026.11457107","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE 17th Latin America Symposium on Circuits and System (LASCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5132708241","display_name":"Luis Eduardo Mendes","orcid":null},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"Luis Eduardo Mendes","raw_affiliation_strings":["Federal University of Rio Grande do Sul (UFRGS) - Institute of Informatics - PGMICRO,Porto Alegre,Brazil"],"affiliations":[{"raw_affiliation_string":"Federal University of Rio Grande do Sul (UFRGS) - Institute of Informatics - PGMICRO,Porto Alegre,Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069385208","display_name":"F\u00e1bio Benevenuti","orcid":"https://orcid.org/0000-0002-0996-9470"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Fabio Benevenuti","raw_affiliation_strings":["Federal University of Rio Grande do Sul (UFRGS) - Institute of Informatics - PGMICRO,Porto Alegre,Brazil"],"affiliations":[{"raw_affiliation_string":"Federal University of Rio Grande do Sul (UFRGS) - Institute of Informatics - PGMICRO,Porto Alegre,Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5132575683","display_name":"Antonio Carlos S. Beck","orcid":null},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Antonio Carlos S. Beck","raw_affiliation_strings":["Federal University of Rio Grande do Sul (UFRGS) - Institute of Informatics - PGMICRO,Porto Alegre,Brazil"],"affiliations":[{"raw_affiliation_string":"Federal University of Rio Grande do Sul (UFRGS) - Institute of Informatics - PGMICRO,Porto Alegre,Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046167370","display_name":"Jos\u00e9 Rodrigo Azambuja","orcid":"https://orcid.org/0000-0002-2627-5075"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Jose Rodrigo Azambuja","raw_affiliation_strings":["Federal University of Rio Grande do Sul (UFRGS) - Institute of Informatics - PGMICRO,Porto Alegre,Brazil"],"affiliations":[{"raw_affiliation_string":"Federal University of Rio Grande do Sul (UFRGS) - Institute of Informatics - PGMICRO,Porto Alegre,Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5132622201","display_name":"Fernanda L. Kastensmidt","orcid":null},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Fernanda L. Kastensmidt","raw_affiliation_strings":["Federal University of Rio Grande do Sul (UFRGS) - Institute of Informatics - PGMICRO,Porto Alegre,Brazil"],"affiliations":[{"raw_affiliation_string":"Federal University of Rio Grande do Sul (UFRGS) - Institute of Informatics - PGMICRO,Porto Alegre,Brazil","institution_ids":["https://openalex.org/I130442723"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5132708241"],"corresponding_institution_ids":["https://openalex.org/I130442723"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.90242818,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.6373999714851379,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.6373999714851379,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.15950000286102295,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.04490000009536743,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.5954999923706055},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5702000260353088},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.511900007724762},{"id":"https://openalex.org/keywords/system-bus","display_name":"System bus","score":0.4726000130176544},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.46050000190734863},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.4496999979019165},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.42250001430511475},{"id":"https://openalex.org/keywords/integrated-design","display_name":"Integrated design","score":0.3824000060558319},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.37560001015663147}],"concepts":[{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6604999899864197},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.5954999923706055},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5702000260353088},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.511900007724762},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4957999885082245},{"id":"https://openalex.org/C136321198","wikidata":"https://www.wikidata.org/wiki/Q2377054","display_name":"System bus","level":2,"score":0.4726000130176544},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.46050000190734863},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.4496999979019165},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.42250001430511475},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.390500009059906},{"id":"https://openalex.org/C2778588580","wikidata":"https://www.wikidata.org/wiki/Q6043060","display_name":"Integrated design","level":2,"score":0.3824000060558319},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3756999969482422},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.37560001015663147},{"id":"https://openalex.org/C2777024059","wikidata":"https://www.wikidata.org/wiki/Q1665471","display_name":"Integration platform","level":2,"score":0.35280001163482666},{"id":"https://openalex.org/C20136886","wikidata":"https://www.wikidata.org/wiki/Q749647","display_name":"Interoperability","level":2,"score":0.3488999903202057},{"id":"https://openalex.org/C2780980858","wikidata":"https://www.wikidata.org/wiki/Q110022","display_name":"Dual (grammatical number)","level":2,"score":0.3465999960899353},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.33809998631477356},{"id":"https://openalex.org/C64270927","wikidata":"https://www.wikidata.org/wiki/Q206924","display_name":"PCI Express","level":3,"score":0.32499998807907104},{"id":"https://openalex.org/C2780395129","wikidata":"https://www.wikidata.org/wiki/Q1128971","display_name":"Rapid prototyping","level":2,"score":0.3224000036716461},{"id":"https://openalex.org/C203315745","wikidata":"https://www.wikidata.org/wiki/Q2235486","display_name":"Control bus","level":3,"score":0.3174000084400177},{"id":"https://openalex.org/C103987645","wikidata":"https://www.wikidata.org/wiki/Q985806","display_name":"Network interface","level":3,"score":0.31630000472068787},{"id":"https://openalex.org/C19527686","wikidata":"https://www.wikidata.org/wiki/Q1665453","display_name":"System integration","level":2,"score":0.3075999915599823},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.3010999858379364},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.2994000017642975},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.2976999878883362},{"id":"https://openalex.org/C2780070844","wikidata":"https://www.wikidata.org/wiki/Q857815","display_name":"Plug and play","level":2,"score":0.28769999742507935},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2793000042438507},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.2736999988555908},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.2736999988555908},{"id":"https://openalex.org/C206345919","wikidata":"https://www.wikidata.org/wiki/Q20380951","display_name":"Resource (disambiguation)","level":2,"score":0.25519999861717224}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/lascas67804.2026.11457107","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lascas67804.2026.11457107","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE 17th Latin America Symposium on Circuits and System (LASCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G1108991687","display_name":null,"funder_award_id":"N629092212014","funder_id":"https://openalex.org/F4320338298","funder_display_name":"Office of Naval Research Global"},{"id":"https://openalex.org/G7124534065","display_name":null,"funder_award_id":"056/2023","funder_id":"https://openalex.org/F4320321992","funder_display_name":"Minist\u00e9rio da Ci\u00eancia, Tecnologia e Inova\u00e7\u00e3o"}],"funders":[{"id":"https://openalex.org/F4320321992","display_name":"Minist\u00e9rio da Ci\u00eancia, Tecnologia e Inova\u00e7\u00e3o","ror":"https://ror.org/050zdnc69"},{"id":"https://openalex.org/F4320338298","display_name":"Office of Naval Research Global","ror":"https://ror.org/00rk2pe57"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W3084147765","https://openalex.org/W4296209134","https://openalex.org/W4315489358","https://openalex.org/W4403279662"],"related_works":[],"abstract_inverted_index":{"The":[0,87,157],"increasing":[1],"demand":[2],"for":[3,153,180],"scalable":[4],"and":[5,37,42,64,95,121,125,139,149,162,174],"energy-efficient":[6],"computing":[7],"platforms":[8],"has":[9,30],"driven":[10],"the":[11,24,27,75,82,90,147,175],"adoption":[12,176],"of":[13,60,77,98,151,177],"chiplet-based":[14,51,154],"design":[15,88,173],"methodologies":[16],"as":[17,123],"an":[18,103,113],"alternative":[19],"to":[20,34,166],"monolithic":[21],"SoCs.":[22],"At":[23],"same":[25],"time,":[26],"RISC-V":[28,78,93,155],"ISA":[29],"gained":[31],"traction":[32],"due":[33],"its":[35],"openness":[36],"modularity,":[38],"enabling":[39],"rapid":[40],"prototyping":[41],"integration":[43,52,76],"into":[44],"heterogeneous":[45],"systems.":[46,156],"A":[47],"key":[48],"challenge":[49],"in":[50,169],"is":[53],"establishing":[54],"a":[55,71,96],"robust":[56],"die-to-die":[57],"interconnect":[58],"capable":[59],"delivering":[61],"high":[62],"bandwidth":[63],"low":[65],"latency":[66],"communication.":[67],"This":[68],"paper":[69],"presents":[70],"case":[72,158],"study":[73,159],"on":[74,131],"SoCs":[79,118],"interconnected":[80,122],"via":[81],"Advanced":[83],"Interface":[84],"Bus":[85],"(AIB).":[86],"leverages":[89],"NoX":[91],"32-bit":[92],"processor":[94],"set":[97],"standard":[99],"peripherals":[100],"integrated":[101],"through":[102],"AXI":[104,143],"crossbar,":[105],"with":[106,128],"communication":[107,163],"extended":[108],"across":[109],"chip":[110],"boundaries":[111],"using":[112],"AXI-to-AIB":[114],"bridge.":[115],"Two":[116],"identical":[117],"were":[119],"implemented":[120],"Leader":[124],"Follower":[126],"chiplets,":[127],"validation":[129],"performed":[130],"FPGA.":[132],"Experimental":[133],"results":[134],"evaluate":[135],"hardware":[136],"resource":[137],"utilization":[138],"throughput":[140],"under":[141],"different":[142],"transaction":[144],"loads,":[145],"demonstrating":[146],"feasibility":[148],"efficiency":[150],"AIB":[152],"highlights":[160],"area":[161],"trade-offs,":[164],"contributing":[165],"ongoing":[167],"efforts":[168],"modular":[170],"multi-die":[171],"system":[172],"open":[178],"standards":[179],"chiplet":[181],"interconnects.":[182]},"counts_by_year":[],"updated_date":"2026-04-09T08:11:56.329763","created_date":"2026-04-02T00:00:00"}
