{"id":"https://openalex.org/W7147067088","doi":"https://doi.org/10.1109/lascas67804.2026.11457105","title":"Analyzing Hardware Accelerators' Reliability: From Design Exploration to Fast Evaluation with Hyperscalers","display_name":"Analyzing Hardware Accelerators' Reliability: From Design Exploration to Fast Evaluation with Hyperscalers","publication_year":2026,"publication_date":"2026-02-24","ids":{"openalex":"https://openalex.org/W7147067088","doi":"https://doi.org/10.1109/lascas67804.2026.11457105"},"language":null,"primary_location":{"id":"doi:10.1109/lascas67804.2026.11457105","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lascas67804.2026.11457105","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE 17th Latin America Symposium on Circuits and System (LASCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5132574647","display_name":"Juan-David Guerrero-Balaguera","orcid":null},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Juan-David Guerrero-Balaguera","raw_affiliation_strings":["Politecnico di Torino,Department of Control and Computer Engineering,Turin,Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Torino,Department of Control and Computer Engineering,Turin,Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5132647511","display_name":"Robert Limas Sierra","orcid":null},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Robert Limas Sierra","raw_affiliation_strings":["Politecnico di Torino,Department of Control and Computer Engineering,Turin,Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Torino,Department of Control and Computer Engineering,Turin,Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5132682845","display_name":"Gustavo Vilar de Farias","orcid":null},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Gustavo Vilar de Farias","raw_affiliation_strings":["Politecnico di Torino,Department of Control and Computer Engineering,Turin,Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Torino,Department of Control and Computer Engineering,Turin,Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5117630132","display_name":"Sergiu-Mohamed Abed","orcid":null},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Sergiu-Mohamed Abed","raw_affiliation_strings":["Politecnico di Torino,Department of Control and Computer Engineering,Turin,Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Torino,Department of Control and Computer Engineering,Turin,Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070821414","display_name":"Ahmet \u00c7a\u011fr\u0131 Ba\u011fbaba","orcid":"https://orcid.org/0000-0001-5251-4378"},"institutions":[{"id":"https://openalex.org/I4210089203","display_name":"Cadence Design Systems (Germany)","ror":"https://ror.org/00d9ep044","country_code":"DE","type":"company","lineage":["https://openalex.org/I4210089203","https://openalex.org/I66217453"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Ahmet Cagri Bagbaba","raw_affiliation_strings":["Cadence Design Systems,Munich,Germany"],"affiliations":[{"raw_affiliation_string":"Cadence Design Systems,Munich,Germany","institution_ids":["https://openalex.org/I4210089203"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5132577227","display_name":"Josie E. Rodriguez Condia","orcid":null},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Josie E. Rodriguez Condia","raw_affiliation_strings":["Politecnico di Torino,Department of Control and Computer Engineering,Turin,Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Torino,Department of Control and Computer Engineering,Turin,Italy","institution_ids":["https://openalex.org/I177477856"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5132574647"],"corresponding_institution_ids":["https://openalex.org/I177477856"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.94849398,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.35019999742507935,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.35019999742507935,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.2232999950647354,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.08089999854564667,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.6489999890327454},{"id":"https://openalex.org/keywords/resilience","display_name":"Resilience (materials science)","score":0.489300012588501},{"id":"https://openalex.org/keywords/space-exploration","display_name":"Space exploration","score":0.43560001254081726},{"id":"https://openalex.org/keywords/enhanced-data-rates-for-gsm-evolution","display_name":"Enhanced Data Rates for GSM Evolution","score":0.43470001220703125},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.4169999957084656},{"id":"https://openalex.org/keywords/space","display_name":"Space (punctuation)","score":0.4092000126838684},{"id":"https://openalex.org/keywords/hardware-acceleration","display_name":"Hardware acceleration","score":0.40119999647140503},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.3499000072479248}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6686999797821045},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.6489999890327454},{"id":"https://openalex.org/C2779585090","wikidata":"https://www.wikidata.org/wiki/Q3457762","display_name":"Resilience (materials science)","level":2,"score":0.489300012588501},{"id":"https://openalex.org/C104060986","wikidata":"https://www.wikidata.org/wiki/Q180046","display_name":"Space exploration","level":2,"score":0.43560001254081726},{"id":"https://openalex.org/C162307627","wikidata":"https://www.wikidata.org/wiki/Q204833","display_name":"Enhanced Data Rates for GSM Evolution","level":2,"score":0.43470001220703125},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.4169999957084656},{"id":"https://openalex.org/C2778572836","wikidata":"https://www.wikidata.org/wiki/Q380933","display_name":"Space (punctuation)","level":2,"score":0.4092000126838684},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.40119999647140503},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.40049999952316284},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.3677999973297119},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3571999967098236},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.3562999963760376},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.3499000072479248},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.34790000319480896},{"id":"https://openalex.org/C155281189","wikidata":"https://www.wikidata.org/wiki/Q3518150","display_name":"Tensor (intrinsic definition)","level":2,"score":0.3449999988079071},{"id":"https://openalex.org/C18762648","wikidata":"https://www.wikidata.org/wiki/Q42213","display_name":"Work (physics)","level":2,"score":0.33410000801086426},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.32850000262260437},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.28380000591278076},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.27489998936653137},{"id":"https://openalex.org/C64346931","wikidata":"https://www.wikidata.org/wiki/Q4519148","display_name":"Functional design","level":2,"score":0.2671000063419342},{"id":"https://openalex.org/C77304879","wikidata":"https://www.wikidata.org/wiki/Q211485","display_name":"Space technology","level":2,"score":0.260699987411499},{"id":"https://openalex.org/C179799912","wikidata":"https://www.wikidata.org/wiki/Q205084","display_name":"Computational complexity theory","level":2,"score":0.25760000944137573},{"id":"https://openalex.org/C12267149","wikidata":"https://www.wikidata.org/wiki/Q282453","display_name":"Support vector machine","level":2,"score":0.2554999887943268},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.25360000133514404},{"id":"https://openalex.org/C119823426","wikidata":"https://www.wikidata.org/wiki/Q184793","display_name":"Computer Aided Design","level":2,"score":0.2533999979496002},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.2529999911785126},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.25200000405311584}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/lascas67804.2026.11457105","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lascas67804.2026.11457105","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE 17th Latin America Symposium on Circuits and System (LASCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1971995819","https://openalex.org/W3016875561","https://openalex.org/W3042964438","https://openalex.org/W3149134903","https://openalex.org/W3188924112","https://openalex.org/W3189398641","https://openalex.org/W4312356560","https://openalex.org/W4382939901","https://openalex.org/W4387064050","https://openalex.org/W4388662247","https://openalex.org/W4392746425","https://openalex.org/W4393041474","https://openalex.org/W4397124197","https://openalex.org/W4399120293","https://openalex.org/W4403278197","https://openalex.org/W4407691307"],"related_works":[],"abstract_inverted_index":{"The":[0],"rising":[1],"density":[2],"and":[3,49,59,67,99,107,117,130],"complexity":[4],"of":[5,47,91,102,127],"domain-specific":[6],"accelerators":[7,55,104],"make":[8],"conventional":[9],"design":[10,48,74],"space":[11,75],"exploration":[12,76],"strategies":[13],"prohibitively":[14],"expensive.":[15],"These":[16],"costs":[17,126],"further":[18],"escalate":[19],"when":[20],"non-functional":[21,100],"properties,":[22],"such":[23,112],"as":[24],"resilience,":[25],"must":[26],"be":[27],"assessed":[28],"for":[29,35,44,56,82],"safety-critical":[30],"applications,":[31],"highlighting":[32],"the":[33,79,89,124],"need":[34],"innovative":[36],"early-stage":[37],"evaluation":[38],"frameworks.":[39],"This":[40],"work":[41],"investigates":[42],"methods":[43],"early":[45,128],"estimation":[46],"resilience":[50],"features":[51],"in":[52],"large":[53,103],"hardware":[54],"edge":[57],"computing":[58],"machine":[60],"learning":[61],"(e.g.,":[62],"vector":[63,84],"processors,":[64],"tensor":[65],"cores,":[66],"stereo":[68],"vision":[69],"engines).":[70],"We":[71,86],"first":[72],"outline":[73],"challenges":[77],"at":[78],"micro-architectural":[80],"level":[81],"configurable":[83],"processors.":[85],"then":[87],"assess":[88],"use":[90],"open-source":[92],"hyperscaler":[93],"frameworks":[94,113],"to":[95,122],"analyze":[96],"fine-grained":[97],"functional":[98],"properties":[101],"via":[105],"simulation":[106],"emulation.":[108],"Results":[109],"show":[110],"that":[111],"are":[114],"feasible":[115],"solutions":[116],"provide":[118],"a":[119],"viable":[120],"path":[121],"reducing":[123],"computational":[125],"characterization":[129],"evaluation.":[131]},"counts_by_year":[],"updated_date":"2026-04-02T13:53:19.096889","created_date":"2026-04-02T00:00:00"}
