{"id":"https://openalex.org/W7147114569","doi":"https://doi.org/10.1109/lascas67804.2026.11457072","title":"An Error-Resilient Area-Efficient Ultra-Low-Power 4-Bit Flash ADC Design with Multi-Vt Transistors","display_name":"An Error-Resilient Area-Efficient Ultra-Low-Power 4-Bit Flash ADC Design with Multi-Vt Transistors","publication_year":2026,"publication_date":"2026-02-24","ids":{"openalex":"https://openalex.org/W7147114569","doi":"https://doi.org/10.1109/lascas67804.2026.11457072"},"language":null,"primary_location":{"id":"doi:10.1109/lascas67804.2026.11457072","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lascas67804.2026.11457072","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE 17th Latin America Symposium on Circuits and System (LASCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5058456300","display_name":"Riyanka Banerjee","orcid":"https://orcid.org/0000-0001-9320-5686"},"institutions":[{"id":"https://openalex.org/I41763900","display_name":"Central Electronics Engineering Research Institute","ror":"https://ror.org/01hh45364","country_code":"IN","type":"facility","lineage":["https://openalex.org/I2799351866","https://openalex.org/I41763900","https://openalex.org/I4210134808","https://openalex.org/I66760702"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Riyanka Banerjee","raw_affiliation_strings":["CSIR - Central Electronics Engineering Research Institute (CEERI),Pilani,India,333031"],"affiliations":[{"raw_affiliation_string":"CSIR - Central Electronics Engineering Research Institute (CEERI),Pilani,India,333031","institution_ids":["https://openalex.org/I41763900"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5132611643","display_name":"Jay Nangia","orcid":null},"institutions":[{"id":"https://openalex.org/I74796645","display_name":"Birla Institute of Technology and Science, Pilani","ror":"https://ror.org/001p3jz28","country_code":"IN","type":"education","lineage":["https://openalex.org/I74796645"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Jay Nangia","raw_affiliation_strings":["Birla Institute of Technology and Science (BITS),Pilani,Rajasthan,India,333031"],"affiliations":[{"raw_affiliation_string":"Birla Institute of Technology and Science (BITS),Pilani,Rajasthan,India,333031","institution_ids":["https://openalex.org/I74796645"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5132596315","display_name":"M. Santosh","orcid":null},"institutions":[{"id":"https://openalex.org/I41763900","display_name":"Central Electronics Engineering Research Institute","ror":"https://ror.org/01hh45364","country_code":"IN","type":"facility","lineage":["https://openalex.org/I2799351866","https://openalex.org/I41763900","https://openalex.org/I4210134808","https://openalex.org/I66760702"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"M. Santosh","raw_affiliation_strings":["CSIR - Central Electronics Engineering Research Institute (CEERI),Pilani,India,333031"],"affiliations":[{"raw_affiliation_string":"CSIR - Central Electronics Engineering Research Institute (CEERI),Pilani,India,333031","institution_ids":["https://openalex.org/I41763900"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011088447","display_name":"Jai Gopal Pandey","orcid":"https://orcid.org/0000-0001-9937-7438"},"institutions":[{"id":"https://openalex.org/I41763900","display_name":"Central Electronics Engineering Research Institute","ror":"https://ror.org/01hh45364","country_code":"IN","type":"facility","lineage":["https://openalex.org/I2799351866","https://openalex.org/I41763900","https://openalex.org/I4210134808","https://openalex.org/I66760702"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Jai Gopal Pandey","raw_affiliation_strings":["CSIR - Central Electronics Engineering Research Institute (CEERI),Pilani,India,333031"],"affiliations":[{"raw_affiliation_string":"CSIR - Central Electronics Engineering Research Institute (CEERI),Pilani,India,333031","institution_ids":["https://openalex.org/I41763900"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5058456300"],"corresponding_institution_ids":["https://openalex.org/I41763900"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.91124877,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"01","last_page":"05"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9873999953269958,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9873999953269958,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.002199999988079071,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.0013000000035390258,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/flash-adc","display_name":"Flash ADC","score":0.7861999869346619},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.742900013923645},{"id":"https://openalex.org/keywords/comparator","display_name":"Comparator","score":0.6022999882698059},{"id":"https://openalex.org/keywords/flash","display_name":"Flash (photography)","score":0.5489000082015991},{"id":"https://openalex.org/keywords/figure-of-merit","display_name":"Figure of merit","score":0.501800000667572},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4683000147342682},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.43880000710487366},{"id":"https://openalex.org/keywords/threshold-voltage","display_name":"Threshold voltage","score":0.35530000925064087}],"concepts":[{"id":"https://openalex.org/C164862427","wikidata":"https://www.wikidata.org/wiki/Q2744647","display_name":"Flash ADC","level":4,"score":0.7861999869346619},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.742900013923645},{"id":"https://openalex.org/C155745195","wikidata":"https://www.wikidata.org/wiki/Q1164179","display_name":"Comparator","level":3,"score":0.6022999882698059},{"id":"https://openalex.org/C2777526259","wikidata":"https://www.wikidata.org/wiki/Q221836","display_name":"Flash (photography)","level":2,"score":0.5489000082015991},{"id":"https://openalex.org/C130277099","wikidata":"https://www.wikidata.org/wiki/Q3676605","display_name":"Figure of merit","level":2,"score":0.501800000667572},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4982999861240387},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.49380001425743103},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4683000147342682},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.43880000710487366},{"id":"https://openalex.org/C195370968","wikidata":"https://www.wikidata.org/wiki/Q1754002","display_name":"Threshold voltage","level":4,"score":0.35530000925064087},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3431999981403351},{"id":"https://openalex.org/C2778422915","wikidata":"https://www.wikidata.org/wiki/Q10302051","display_name":"Converters","level":3,"score":0.3407999873161316},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.32820001244544983},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3075000047683716},{"id":"https://openalex.org/C128624480","wikidata":"https://www.wikidata.org/wiki/Q1504817","display_name":"Low voltage","level":3,"score":0.2903999984264374},{"id":"https://openalex.org/C111106434","wikidata":"https://www.wikidata.org/wiki/Q1072430","display_name":"Die (integrated circuit)","level":2,"score":0.2897999882698059},{"id":"https://openalex.org/C44351266","wikidata":"https://www.wikidata.org/wiki/Q1465532","display_name":"Voltage reference","level":3,"score":0.2766999900341034},{"id":"https://openalex.org/C63651839","wikidata":"https://www.wikidata.org/wiki/Q478566","display_name":"Input offset voltage","level":5,"score":0.27559998631477356},{"id":"https://openalex.org/C140779682","wikidata":"https://www.wikidata.org/wiki/Q210868","display_name":"Sampling (signal processing)","level":3,"score":0.27469998598098755},{"id":"https://openalex.org/C129014197","wikidata":"https://www.wikidata.org/wiki/Q906544","display_name":"Power semiconductor device","level":3,"score":0.25189998745918274}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/lascas67804.2026.11457072","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lascas67804.2026.11457072","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE 17th Latin America Symposium on Circuits and System (LASCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.7957307696342468}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1615941610","https://openalex.org/W1979511872","https://openalex.org/W1990446740","https://openalex.org/W2016791588","https://openalex.org/W2150363350","https://openalex.org/W2172236250","https://openalex.org/W2313921896","https://openalex.org/W2609552772","https://openalex.org/W2785229656","https://openalex.org/W2944515859","https://openalex.org/W3011254007","https://openalex.org/W3162750047","https://openalex.org/W4226118297","https://openalex.org/W4309781547","https://openalex.org/W4385187379","https://openalex.org/W4391826829","https://openalex.org/W4393973533","https://openalex.org/W4411727560","https://openalex.org/W4414747434"],"related_works":[],"abstract_inverted_index":{"In":[0,12],"high-speed,":[1],"low-resolution":[2],"conversion":[3],"applications,":[4],"Flash":[5,17,57],"analog-to-digital":[6],"converters":[7],"(ADCs)":[8],"are":[9],"most":[10],"suitable.":[11],"the":[13],"proposed":[14,83],"work,":[15],"a":[16,86,93,116,128,144],"ADC":[18,58],"is":[19],"designed":[20,56],"using":[21],"multithreshold":[22],"transistors":[23,33,37,41,46,48,63],"offered":[24],"in":[25],"sub-micron":[26],"CMOS":[27],"technology,":[28],"effectively":[29],"leveraging":[30],"low-threshold":[31],"voltage":[32,36,40,45],"(LVT),":[34],"nominal-threshold":[35],"(NVT),":[38],"regular-threshold":[39],"(RVT),":[42],"and":[43,52,78,104,143],"high-threshold":[44],"(HVT)":[47],"to":[49,66],"optimize":[50],"performance":[51,113],"power":[53],"efficiency.":[54],"The":[55,82],"architecture":[59],"incorporates":[60],"calibrated":[61],"multi-threshold":[62],"based":[64],"comparators":[65],"balance":[67],"between":[68],"gain-bandwidth":[69],"trade-off,":[70],"reduced":[71],"area,":[72],"desired":[73],"figure":[74],"of":[75,89,121,125,132,138,141,147],"merit":[76],"(FoM),":[77],"ensure":[79],"bubble-free":[80],"encoding.":[81],"design":[84],"achieves":[85],"sampling":[87],"rate":[88],"2":[90],"MS/s":[91],"at":[92],"1.2":[94],"V":[95],"supply,":[96],"consumes":[97],"only":[98],"<tex":[99,105],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[100,106],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">$17.48":[101],"\\mu":[102,108],"\\mathrm{W}$</tex>":[103],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">$478.6788":[107],"\\mathrm{m}^{2}$</tex>":[109],"active":[110],"area.":[111],"Key":[112],"metrics":[114],"include":[115],"peak":[117],"differential":[118],"non-linearity":[119],"(DNL)":[120],"0.4":[122],"LSB,":[123],"INL":[124],"0.7":[126],"LSB":[127],"signal-to-noise-and-distortion":[129],"ratio":[130],"(SNDR)":[131],"22.83":[133],"dB,":[134],"an":[135],"effective":[136],"number":[137],"bits":[139],"(ENOB)":[140],"3.5,":[142],"resulting":[145],"FoM":[146],"273.13":[148],"fJ/conversion-step.":[149]},"counts_by_year":[],"updated_date":"2026-04-02T13:53:19.096889","created_date":"2026-04-02T00:00:00"}
