{"id":"https://openalex.org/W4395662252","doi":"https://doi.org/10.1109/lascas60203.2024.10506182","title":"Transition from Synchronous to Asynchronous Systems with Minimal Logic Changes","display_name":"Transition from Synchronous to Asynchronous Systems with Minimal Logic Changes","publication_year":2024,"publication_date":"2024-02-27","ids":{"openalex":"https://openalex.org/W4395662252","doi":"https://doi.org/10.1109/lascas60203.2024.10506182"},"language":"en","primary_location":{"id":"doi:10.1109/lascas60203.2024.10506182","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/lascas60203.2024.10506182","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE 15th Latin America Symposium on Circuits and Systems (LASCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101800688","display_name":"Juan Carlos Garcia Lopez","orcid":"https://orcid.org/0009-0007-0766-5709"},"institutions":[{"id":"https://openalex.org/I68368234","display_name":"Centro de Investigaci\u00f3n y de Estudios Avanzados del Instituto Polit\u00e9cnico Nacional","ror":"https://ror.org/009eqmr18","country_code":"MX","type":"facility","lineage":["https://openalex.org/I59361560","https://openalex.org/I68368234"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"Juan Carlos Garcia Lopez","raw_affiliation_strings":["CINVESTAV-GDL,Dept. of Electrical Engineering,Zapopan,Jalisco,Mexico","Dept. of Electrical Engineering, CINVESTAV-GDL, Zapopan, Jalisco, Mexico"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CINVESTAV-GDL,Dept. of Electrical Engineering,Zapopan,Jalisco,Mexico","institution_ids":["https://openalex.org/I68368234"]},{"raw_affiliation_string":"Dept. of Electrical Engineering, CINVESTAV-GDL, Zapopan, Jalisco, Mexico","institution_ids":["https://openalex.org/I68368234"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060102766","display_name":"Susana Ortega Cisneros","orcid":"https://orcid.org/0000-0001-6646-1529"},"institutions":[{"id":"https://openalex.org/I68368234","display_name":"Centro de Investigaci\u00f3n y de Estudios Avanzados del Instituto Polit\u00e9cnico Nacional","ror":"https://ror.org/009eqmr18","country_code":"MX","type":"facility","lineage":["https://openalex.org/I59361560","https://openalex.org/I68368234"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"S. Ortega-Cisneros","raw_affiliation_strings":["CINVESTAV-GDL,Dept. of Electrical Engineering,Zapopan,Jalisco,Mexico","Dept. of Electrical Engineering, CINVESTAV-GDL, Zapopan, Jalisco, Mexico"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CINVESTAV-GDL,Dept. of Electrical Engineering,Zapopan,Jalisco,Mexico","institution_ids":["https://openalex.org/I68368234"]},{"raw_affiliation_string":"Dept. of Electrical Engineering, CINVESTAV-GDL, Zapopan, Jalisco, Mexico","institution_ids":["https://openalex.org/I68368234"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013897565","display_name":"Emilio Isaac Baungarten-Leon","orcid":"https://orcid.org/0000-0001-6243-219X"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Emilio Isaac Baungarten-Leon","raw_affiliation_strings":["CINVESTAV-GDL, Universidad Autó noma de Guadalajara,Dept. of Electrical Engineering,Zapopan,Jalisco,Mexico"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CINVESTAV-GDL, Universidad Autó noma de Guadalajara,Dept. of Electrical Engineering,Zapopan,Jalisco,Mexico","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5095902705","display_name":"M. V\u00e1zquez-Robles","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"M. V\u00e1zquez-Robles","raw_affiliation_strings":["Instituto de Ingenieria y Tecnología, Universidad Autónoma de Ciudad Juárez Cd.,Juárez,México"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto de Ingenieria y Tecnología, Universidad Autónoma de Ciudad Juárez Cd.,Juárez,México","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026852819","display_name":"Jorge Rivera","orcid":"https://orcid.org/0000-0003-0978-2224"},"institutions":[{"id":"https://openalex.org/I68368234","display_name":"Centro de Investigaci\u00f3n y de Estudios Avanzados del Instituto Polit\u00e9cnico Nacional","ror":"https://ror.org/009eqmr18","country_code":"MX","type":"facility","lineage":["https://openalex.org/I59361560","https://openalex.org/I68368234"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"Jorge Rivera Dom\u00ednguez","raw_affiliation_strings":["CINVESTAV-GDL,Dept. of Electrical Engineering,Zapopan,Jalisco,Mexico","Dept. of Electrical Engineering, CINVESTAV-GDL, Zapopan, Jalisco, Mexico"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CINVESTAV-GDL,Dept. of Electrical Engineering,Zapopan,Jalisco,Mexico","institution_ids":["https://openalex.org/I68368234"]},{"raw_affiliation_string":"Dept. of Electrical Engineering, CINVESTAV-GDL, Zapopan, Jalisco, Mexico","institution_ids":["https://openalex.org/I68368234"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.03590063,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.8645602464675903},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.7886606454849243},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.7413794994354248},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6534949541091919},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.6444119811058044},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5313779711723328},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5209314227104187},{"id":"https://openalex.org/keywords/asynchronous-system","display_name":"Asynchronous system","score":0.5085417032241821},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4487648010253906},{"id":"https://openalex.org/keywords/synchronizer","display_name":"Synchronizer","score":0.44850459694862366},{"id":"https://openalex.org/keywords/von-neumann-architecture","display_name":"Von Neumann architecture","score":0.4273127019405365},{"id":"https://openalex.org/keywords/perspective","display_name":"Perspective (graphical)","score":0.416523814201355},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3970894515514374},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3786962628364563},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.24866831302642822},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.21903100609779358},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19348809123039246},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11483359336853027},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.10774031281471252},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.09106582403182983}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.8645602464675903},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.7886606454849243},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.7413794994354248},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6534949541091919},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.6444119811058044},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5313779711723328},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5209314227104187},{"id":"https://openalex.org/C7923308","wikidata":"https://www.wikidata.org/wiki/Q4812211","display_name":"Asynchronous system","level":5,"score":0.5085417032241821},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4487648010253906},{"id":"https://openalex.org/C66727535","wikidata":"https://www.wikidata.org/wiki/Q7662199","display_name":"Synchronizer","level":2,"score":0.44850459694862366},{"id":"https://openalex.org/C80469333","wikidata":"https://www.wikidata.org/wiki/Q189088","display_name":"Von Neumann architecture","level":2,"score":0.4273127019405365},{"id":"https://openalex.org/C12713177","wikidata":"https://www.wikidata.org/wiki/Q1900281","display_name":"Perspective (graphical)","level":2,"score":0.416523814201355},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3970894515514374},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3786962628364563},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.24866831302642822},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.21903100609779358},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19348809123039246},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11483359336853027},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.10774031281471252},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.09106582403182983},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/lascas60203.2024.10506182","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/lascas60203.2024.10506182","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE 15th Latin America Symposium on Circuits and Systems (LASCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W2036372420","https://openalex.org/W2064639253","https://openalex.org/W2150872535","https://openalex.org/W2919987885","https://openalex.org/W2941371147","https://openalex.org/W3006136417","https://openalex.org/W3082598508","https://openalex.org/W4229441806","https://openalex.org/W4237783448","https://openalex.org/W4378966492","https://openalex.org/W4386265868"],"related_works":["https://openalex.org/W60393894","https://openalex.org/W158833317","https://openalex.org/W2325117947","https://openalex.org/W628161287","https://openalex.org/W1984298705","https://openalex.org/W794031490","https://openalex.org/W4247130854","https://openalex.org/W2349909378","https://openalex.org/W1482079447","https://openalex.org/W2127795343"],"abstract_inverted_index":{"This":[0,92],"paper":[1],"examines":[2],"the":[3,15,33,43,57,61,69,99,111],"transition":[4],"from":[5],"syn-chronous":[6],"to":[7,14,54],"asynchronous":[8,79],"microprocessor":[9,40],"systems":[10,80],"as":[11],"a":[12,39,50,55,95],"response":[13],"physical":[16],"and":[17,27,108],"technological":[18],"limits":[19],"reached":[20],"in":[21,38,60,72,87],"terms":[22,88],"of":[23,32,89,101],"transistor":[24],"size":[25],"reduction":[26],"internal":[28],"circuitry.":[29],"The":[30],"implementation":[31],"delay-insensitive,":[34],"dual-rail,":[35],"4-phase":[36],"methodology":[37],"based":[41],"on":[42],"von":[44],"Neumann":[45],"architecture":[46],"is":[47],"studied,":[48],"using":[49],"technique":[51],"that":[52,78],"reduces":[53],"minimum":[56],"changes":[58],"required":[59],"register":[62],"transfer":[63],"level":[64],"(RTL)":[65],"design,":[66],"while":[67],"pre-serving":[68],"designs":[70],"used":[71],"synchronous":[73,83],"logic.":[74],"Simulation":[75],"results":[76],"show":[77],"outperform":[81],"their":[82],"counterparts":[84],"by":[85],"90.9%":[86],"power":[90],"consumption.":[91],"approach":[93],"represents":[94],"promising":[96],"perspective":[97],"for":[98,110],"evolution":[100],"digital":[102],"technology,":[103],"opening":[104],"up":[105],"new":[106],"opportunities":[107],"challenges":[109],"future.":[112]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}