{"id":"https://openalex.org/W4395685301","doi":"https://doi.org/10.1109/lascas60203.2024.10506121","title":"A Structured Approach for Embedded Memory Integration of Emerging Memory Technologies","display_name":"A Structured Approach for Embedded Memory Integration of Emerging Memory Technologies","publication_year":2024,"publication_date":"2024-02-27","ids":{"openalex":"https://openalex.org/W4395685301","doi":"https://doi.org/10.1109/lascas60203.2024.10506121"},"language":"en","primary_location":{"id":"doi:10.1109/lascas60203.2024.10506121","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lascas60203.2024.10506121","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE 15th Latin America Symposium on Circuits and Systems (LASCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5056540006","display_name":"Stefan Pechmann","orcid":"https://orcid.org/0000-0001-6890-3378"},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Stefan Pechmann","raw_affiliation_strings":["Technical University of Munich,Chair of Micro- and Nanosystems Technology,Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technical University of Munich,Chair of Micro- and Nanosystems Technology,Germany","institution_ids":["https://openalex.org/I62916508"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5092691365","display_name":"Thorsten Sp\u00e4tling","orcid":null},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Thorsten Sp\u00e4tling","raw_affiliation_strings":["Technical University of Munich,Chair of Micro- and Nanosystems Technology,Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technical University of Munich,Chair of Micro- and Nanosystems Technology,Germany","institution_ids":["https://openalex.org/I62916508"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069006979","display_name":"Peter Reichel","orcid":"https://orcid.org/0000-0001-7149-8238"},"institutions":[{"id":"https://openalex.org/I4210095661","display_name":"Fraunhofer Institute for Integrated Circuits IIS, Division Engineering of Adaptive Systems EAS","ror":"https://ror.org/00s5yp124","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4210095661","https://openalex.org/I4210124274","https://openalex.org/I4923324"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Peter Reichel","raw_affiliation_strings":["Fraunhofer Institute for Integrated Circuits (IIS),Division Engineering of Adaptive Systems EAS,Dresden,Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fraunhofer Institute for Integrated Circuits (IIS),Division Engineering of Adaptive Systems EAS,Dresden,Germany","institution_ids":["https://openalex.org/I4210095661"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039674907","display_name":"Roland M\u00fcller","orcid":"https://orcid.org/0000-0003-0394-1650"},"institutions":[{"id":"https://openalex.org/I4210124274","display_name":"Fraunhofer Institute for Integrated Circuits","ror":"https://ror.org/024ape423","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4210124274","https://openalex.org/I4923324"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Roland M\u00fcller","raw_affiliation_strings":["Fraunhofer Institute for Integrated Circuits (IIS), Advanced Analog Circuits,Erlangen,Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fraunhofer Institute for Integrated Circuits (IIS), Advanced Analog Circuits,Erlangen,Germany","institution_ids":["https://openalex.org/I4210124274"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5034209342","display_name":"Amelie Hagelauer","orcid":"https://orcid.org/0000-0001-9113-9531"},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Amelie Hagelauer","raw_affiliation_strings":["Technical University of Munich,Chair of Micro- and Nanosystems Technology,Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technical University of Munich,Chair of Micro- and Nanosystems Technology,Germany","institution_ids":["https://openalex.org/I62916508"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.1856,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.45850684,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7125481367111206},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.4761533737182617},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.4503820538520813},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.4493647813796997},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.43285852670669556},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4071246087551117},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.2846193015575409},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.22497963905334473}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7125481367111206},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.4761533737182617},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.4503820538520813},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.4493647813796997},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.43285852670669556},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4071246087551117},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.2846193015575409},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.22497963905334473}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/lascas60203.2024.10506121","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lascas60203.2024.10506121","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE 15th Latin America Symposium on Circuits and Systems (LASCAS)","raw_type":"proceedings-article"},{"id":"pmh:oai:publica.fraunhofer.de:publica/468466","is_oa":false,"landing_page_url":"https://publica.fraunhofer.de/handle/publica/468466","pdf_url":null,"source":{"id":"https://openalex.org/S4306400318","display_name":"Fraunhofer-Publica (Fraunhofer-Gesellschaft)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4923324","host_organization_name":"Fraunhofer-Gesellschaft","host_organization_lineage":["https://openalex.org/I4923324"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"conference paper"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.4300000071525574}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":31,"referenced_works":["https://openalex.org/W2146245483","https://openalex.org/W2164148798","https://openalex.org/W2433248078","https://openalex.org/W2565428989","https://openalex.org/W2604267591","https://openalex.org/W2769084511","https://openalex.org/W2775996013","https://openalex.org/W2794194363","https://openalex.org/W2942764887","https://openalex.org/W2944651134","https://openalex.org/W2945899269","https://openalex.org/W2949588176","https://openalex.org/W2953472377","https://openalex.org/W3018945530","https://openalex.org/W3023138692","https://openalex.org/W3033941112","https://openalex.org/W3046920646","https://openalex.org/W3107757569","https://openalex.org/W3125586476","https://openalex.org/W3157815942","https://openalex.org/W3158701691","https://openalex.org/W3193404801","https://openalex.org/W3216135167","https://openalex.org/W3217323523","https://openalex.org/W4229439741","https://openalex.org/W4281559874","https://openalex.org/W4292874288","https://openalex.org/W4304140701","https://openalex.org/W4312424371","https://openalex.org/W6802576059","https://openalex.org/W6804142272"],"related_works":["https://openalex.org/W4232117715","https://openalex.org/W2561005478","https://openalex.org/W2079019992","https://openalex.org/W2738228043","https://openalex.org/W2199439667","https://openalex.org/W2546565930","https://openalex.org/W3048967625","https://openalex.org/W1554378476","https://openalex.org/W4248614727","https://openalex.org/W2296275612"],"abstract_inverted_index":{"In":[0,21],"this":[1],"paper":[2],"we":[3],"present":[4],"a":[5,25,65,72,90],"structured":[6],"approach":[7,108],"to":[8,23,29,55,58,78,95],"make":[9],"emerging":[10],"memory":[11,35,48,67,76,81,101,127],"technologies":[12],"usable":[13],"in":[14,37,89,102],"integrated,":[15],"electrical":[16],"systems":[17],"as":[18,99,129],"embedded":[19,100],"memory.":[20],"order":[22],"reach":[24],"necessary":[26],"abstraction":[27],"level":[28],"enable":[30,96],"the":[31,42,62,97,110,118],"usage":[32],"of":[33,44,61,64,112],"novel":[34],"cells,":[36],"our":[38,107],"case":[39],"shown":[40],"at":[41],"example":[43,111],"resistive":[45],"random":[46],"access":[47],"(RRAM),":[49],"several":[50],"steps":[51,70],"must":[52],"be":[53,56,122],"realized":[54],"able":[57],"take":[59],"advantage":[60],"benefits":[63],"new":[66],"technology.":[68],"Those":[69],"constitute":[71],"transition":[73],"from":[74],"stand-alone":[75],"device":[77],"usable,":[79],"configurable":[80],"arrays":[82],"with":[83],"read":[84],"and":[85],"programming":[86],"ability,":[87],"included":[88],"digital":[91],"standard":[92],"cell":[93],"grid":[94],"application":[98],"integrated":[103],"systems.":[104],"We":[105],"demonstrate":[106],"on":[109],"1-":[113],"Transistor-I-Resistor":[114],"(1TIR)":[115],"RRAM,":[116],"but":[117],"general":[119],"methodology":[120],"can":[121],"used":[123],"for":[124],"other":[125],"evolving":[126],"technologies,":[128],"well.":[130]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
