{"id":"https://openalex.org/W3016377364","doi":"https://doi.org/10.1109/lascas45839.2020.9069031","title":"Evaluating Cell Library Sizing Methodologies for Ultra-Low Power Near-Threshold Operation in Bulk CMOS","display_name":"Evaluating Cell Library Sizing Methodologies for Ultra-Low Power Near-Threshold Operation in Bulk CMOS","publication_year":2020,"publication_date":"2020-02-01","ids":{"openalex":"https://openalex.org/W3016377364","doi":"https://doi.org/10.1109/lascas45839.2020.9069031","mag":"3016377364"},"language":"en","primary_location":{"id":"doi:10.1109/lascas45839.2020.9069031","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lascas45839.2020.9069031","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE 11th Latin American Symposium on Circuits &amp; Systems (LASCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5071847137","display_name":"Rodrigo N. Wuerdig","orcid":null},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"Rodrigo N. Wuerdig","raw_affiliation_strings":["Informatics Institute - PGMICRO, Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil"],"affiliations":[{"raw_affiliation_string":"Informatics Institute - PGMICRO, Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048165540","display_name":"Vitor G. Lima","orcid":null},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Vitor G. Lima","raw_affiliation_strings":["Informatics Institute - PGMICRO, Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil"],"affiliations":[{"raw_affiliation_string":"Informatics Institute - PGMICRO, Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081693987","display_name":"Filipe D. Baumgratz","orcid":"https://orcid.org/0000-0001-6720-0646"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Filipe Baumgratz","raw_affiliation_strings":["Informatics Institute - PGMICRO, Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil"],"affiliations":[{"raw_affiliation_string":"Informatics Institute - PGMICRO, Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030974893","display_name":"Rafael Soares","orcid":"https://orcid.org/0000-0001-9493-7272"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Rafael Soares","raw_affiliation_strings":["Federal University of Pelotas (UFPEL), Pelotas, Brazil"],"affiliations":[{"raw_affiliation_string":"Federal University of Pelotas (UFPEL), Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5046426137","display_name":"S\u00e9rgio Bampi","orcid":"https://orcid.org/0000-0002-9018-6309"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Sergio Bampi","raw_affiliation_strings":["Informatics Institute - PGMICRO, Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil"],"affiliations":[{"raw_affiliation_string":"Informatics Institute - PGMICRO, Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5071847137"],"corresponding_institution_ids":["https://openalex.org/I130442723"],"apc_list":null,"apc_paid":null,"fwci":0.1027,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.40094702,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.8539984822273254},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.8517057299613953},{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.6854074597358704},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.6446676254272461},{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.5310860872268677},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4979362487792969},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.4900270700454712},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4883372485637665},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.47074586153030396},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4674431085586548},{"id":"https://openalex.org/keywords/energy","display_name":"Energy (signal processing)","score":0.43406182527542114},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.4320327341556549},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.43129175901412964},{"id":"https://openalex.org/keywords/energy-consumption","display_name":"Energy consumption","score":0.4286206066608429},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3578457832336426},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3013231158256531},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.30033278465270996},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2959885001182556},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.20012789964675903},{"id":"https://openalex.org/keywords/chemistry","display_name":"Chemistry","score":0.11393755674362183}],"concepts":[{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.8539984822273254},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.8517057299613953},{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.6854074597358704},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.6446676254272461},{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.5310860872268677},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4979362487792969},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.4900270700454712},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4883372485637665},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.47074586153030396},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4674431085586548},{"id":"https://openalex.org/C186370098","wikidata":"https://www.wikidata.org/wiki/Q442787","display_name":"Energy (signal processing)","level":2,"score":0.43406182527542114},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4320327341556549},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.43129175901412964},{"id":"https://openalex.org/C2780165032","wikidata":"https://www.wikidata.org/wiki/Q16869822","display_name":"Energy consumption","level":2,"score":0.4286206066608429},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3578457832336426},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3013231158256531},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.30033278465270996},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2959885001182556},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.20012789964675903},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.11393755674362183},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C178790620","wikidata":"https://www.wikidata.org/wiki/Q11351","display_name":"Organic chemistry","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/lascas45839.2020.9069031","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lascas45839.2020.9069031","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE 11th Latin American Symposium on Circuits &amp; Systems (LASCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8999999761581421}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2055857026","https://openalex.org/W2075778001","https://openalex.org/W2084371343","https://openalex.org/W2089999409","https://openalex.org/W2157683079","https://openalex.org/W2563060100","https://openalex.org/W2749751536","https://openalex.org/W2763925543","https://openalex.org/W2793306380"],"related_works":["https://openalex.org/W4386261925","https://openalex.org/W2048420745","https://openalex.org/W2082944690","https://openalex.org/W2263373136","https://openalex.org/W1914349328","https://openalex.org/W2160067645","https://openalex.org/W2023334077","https://openalex.org/W2005494397","https://openalex.org/W2104885411","https://openalex.org/W2339836056"],"abstract_inverted_index":{"A":[0],"systematic":[1],"evaluation":[2],"of":[3,12,72],"different":[4,26,80],"transistor":[5],"sizing":[6],"methodologies":[7,21],"for":[8,50,58,68,109,131,164],"near-threshold":[9],"(NTV)":[10],"operation":[11],"CMOS":[13,63,137,148],"standard":[14],"cell":[15,93],"libraries":[16],"is":[17,44,66],"presented":[18],"herein.":[19],"The":[20,140],"are":[22],"developed":[23],"to":[24,46,146,160],"correlate":[25],"library":[27],"design":[28],"optimizing":[29,47],"goals,":[30],"such":[31],"as":[32,150,156],"area,":[33],"maximum":[34,128],"attainable":[35],"frequency,":[36],"energy":[37,129,162],"consumption,":[38],"and":[39,76,83,86],"symmetric":[40],"transition":[41],"slews.":[42],"Consideration":[43],"given":[45],"NTV":[48],"cells":[49,73],"the":[51,98,127,134,154],"Minimum-Energy":[52],"V":[53],"<sub":[54,101,105],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[55,102,106],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">DD</sub>":[56],"supply":[57],"a":[59,69,91,119,157],"bulk":[60],"40":[61,135],"nm":[62,136],"technology.":[64],"Sizing":[65],"optimized":[67],"small":[70],"set":[71],"(NOR,":[74],"NAND,":[75],"inverters":[77],"at":[78,118],"three":[79],"drive":[81],"strengths),":[82],"energy,":[84],"delay,":[85],"area":[87],"results":[88,96,152],"compared":[89],"against":[90],"commercial":[92],"library.":[94],"Our":[95],"establish":[97,153],"best":[99],"W":[100],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">pmos</sub>":[103],"/W":[104],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">nmos</sub>":[107],"ratio":[108],"each":[110],"defined":[111],"trade-off":[112],"(energy-delay,":[113],"area-delay,":[114],"slew-rates)":[115],"while":[116],"operating":[117],"low-supply,":[120],"around":[121],"300":[122],"mV.":[123],"This":[124],"voltage":[125],"enables":[126],"efficiency":[130,163],"logic":[132],"in":[133],"technology":[138],"considered.":[139],"proposed":[141],"method":[142],"can":[143],"be":[144],"applied":[145],"any":[147],"technology,":[149],"our":[151],"methodology":[155],"simple":[158],"approach":[159],"enhance":[161],"NTV.":[165]},"counts_by_year":[{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}