{"id":"https://openalex.org/W3016960227","doi":"https://doi.org/10.1109/lascas45839.2020.9068995","title":"A Flexible Debugger for a RISC-V Based 32-bit System-on-Chip","display_name":"A Flexible Debugger for a RISC-V Based 32-bit System-on-Chip","publication_year":2020,"publication_date":"2020-02-01","ids":{"openalex":"https://openalex.org/W3016960227","doi":"https://doi.org/10.1109/lascas45839.2020.9068995","mag":"3016960227"},"language":"en","primary_location":{"id":"doi:10.1109/lascas45839.2020.9068995","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lascas45839.2020.9068995","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083795735","display_name":"Wilmer Ramirez","orcid":null},"institutions":[{"id":"https://openalex.org/I115684694","display_name":"Industrial University of Santander","ror":"https://ror.org/00xc1d948","country_code":"CO","type":"education","lineage":["https://openalex.org/I115684694"]}],"countries":["CO"],"is_corresponding":false,"raw_author_name":"Wilmer Ramirez","raw_affiliation_strings":["Integrated Systems Research Group OnChip, Universidad Industrial de Santander, Bucaramanga, Colombia","Universidad Industrial de Santander, Integrated Systems Research Group - OnChip, Bucaramanga,Colombia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Systems Research Group OnChip, Universidad Industrial de Santander, Bucaramanga, Colombia","institution_ids":["https://openalex.org/I115684694"]},{"raw_affiliation_string":"Universidad Industrial de Santander, Integrated Systems Research Group - OnChip, Bucaramanga,Colombia","institution_ids":["https://openalex.org/I115684694"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014526006","display_name":"Marco Sarmiento","orcid":"https://orcid.org/0000-0002-3544-8839"},"institutions":[{"id":"https://openalex.org/I115684694","display_name":"Industrial University of Santander","ror":"https://ror.org/00xc1d948","country_code":"CO","type":"education","lineage":["https://openalex.org/I115684694"]}],"countries":["CO"],"is_corresponding":false,"raw_author_name":"Marco Sarmiento","raw_affiliation_strings":["Integrated Systems Research Group OnChip, Universidad Industrial de Santander, Bucaramanga, Colombia","Universidad Industrial de Santander, Integrated Systems Research Group - OnChip, Bucaramanga,Colombia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Systems Research Group OnChip, Universidad Industrial de Santander, Bucaramanga, Colombia","institution_ids":["https://openalex.org/I115684694"]},{"raw_affiliation_string":"Universidad Industrial de Santander, Integrated Systems Research Group - OnChip, Bucaramanga,Colombia","institution_ids":["https://openalex.org/I115684694"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5070510631","display_name":"Elkim Roa","orcid":"https://orcid.org/0000-0003-0290-7493"},"institutions":[{"id":"https://openalex.org/I115684694","display_name":"Industrial University of Santander","ror":"https://ror.org/00xc1d948","country_code":"CO","type":"education","lineage":["https://openalex.org/I115684694"]}],"countries":["CO"],"is_corresponding":false,"raw_author_name":"Elkim Roa","raw_affiliation_strings":["Integrated Systems Research Group OnChip, Universidad Industrial de Santander, Bucaramanga, Colombia","Universidad Industrial de Santander, Integrated Systems Research Group - OnChip, Bucaramanga,Colombia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Systems Research Group OnChip, Universidad Industrial de Santander, Bucaramanga, Colombia","institution_ids":["https://openalex.org/I115684694"]},{"raw_affiliation_string":"Universidad Industrial de Santander, Integrated Systems Research Group - OnChip, Bucaramanga,Colombia","institution_ids":["https://openalex.org/I115684694"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I115684694"],"apc_list":null,"apc_paid":null,"fwci":0.6483,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.71395078,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.9372316598892212},{"id":"https://openalex.org/keywords/background-debug-mode-interface","display_name":"Background debug mode interface","score":0.8401939868927002},{"id":"https://openalex.org/keywords/debugger","display_name":"Debugger","score":0.8387993574142456},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.7733696699142456},{"id":"https://openalex.org/keywords/observability","display_name":"Observability","score":0.7242358922958374},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7170729637145996},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.6114386320114136},{"id":"https://openalex.org/keywords/arm-architecture","display_name":"ARM architecture","score":0.5416264533996582},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.5176530480384827},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4160902500152588},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.32574108242988586},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3201172947883606},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.30516648292541504}],"concepts":[{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.9372316598892212},{"id":"https://openalex.org/C124774103","wikidata":"https://www.wikidata.org/wiki/Q4839640","display_name":"Background debug mode interface","level":3,"score":0.8401939868927002},{"id":"https://openalex.org/C2778485113","wikidata":"https://www.wikidata.org/wiki/Q193231","display_name":"Debugger","level":3,"score":0.8387993574142456},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.7733696699142456},{"id":"https://openalex.org/C36299963","wikidata":"https://www.wikidata.org/wiki/Q1369844","display_name":"Observability","level":2,"score":0.7242358922958374},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7170729637145996},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.6114386320114136},{"id":"https://openalex.org/C26771161","wikidata":"https://www.wikidata.org/wiki/Q16980","display_name":"ARM architecture","level":2,"score":0.5416264533996582},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.5176530480384827},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4160902500152588},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.32574108242988586},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3201172947883606},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.30516648292541504},{"id":"https://openalex.org/C28826006","wikidata":"https://www.wikidata.org/wiki/Q33521","display_name":"Applied mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/lascas45839.2020.9068995","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lascas45839.2020.9068995","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.44999998807907104,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2000905221","https://openalex.org/W2068239131","https://openalex.org/W2134518125","https://openalex.org/W2596578331","https://openalex.org/W2921148081","https://openalex.org/W4231486519"],"related_works":["https://openalex.org/W2366922255","https://openalex.org/W2379522957","https://openalex.org/W2170167243","https://openalex.org/W2086553023","https://openalex.org/W4252104361","https://openalex.org/W2062651468","https://openalex.org/W1917409762","https://openalex.org/W4248152965","https://openalex.org/W2540138467","https://openalex.org/W2136703656"],"abstract_inverted_index":{"Complex":[0],"system-on-chip":[1],"(SoC)":[2],"demands":[3],"to":[4,8,62,70,73,93],"integrate":[5],"debugging":[6,60,83,104,107,141],"systems":[7,19],"control":[9,64],"and":[10,25,65,72,99,127],"monitor":[11,71],"the":[12,32,36,94,102,140,146],"internal":[13],"behavior":[14],"for":[15,85],"post-silicon":[16],"testing.":[17],"Debugging":[18],"must":[20,28,41],"not":[21],"only":[22],"provide":[23],"run-control":[24],"observability;":[26],"they":[27],"also":[29],"allow":[30],"analyzing":[31],"operations":[33],"performed":[34,92],"within":[35],"SoC.":[37],"The":[38,106,129],"analysis":[39,52],"capability":[40],"be":[42],"non-intrusive":[43],"with":[44,115],"a":[45,82,112,116,134],"flexible":[46],"filtering":[47],"option,":[48],"followed":[49],"by":[50],"an":[51,121,124],"performing":[53],"stage.":[54],"Although":[55],"some":[56],"reported":[57],"works":[58],"address":[59],"methods":[61],"perform":[63],"observability,":[66],"details":[67],"about":[68],"how":[69],"analyze":[74],"SoC":[75,114,130,148],"activity":[76],"are":[77],"scarce.":[78],"Here,":[79],"we":[80],"propose":[81],"platform":[84,95,108,142],"post-silicon.":[86],"This":[87],"work":[88],"reports":[89],"experimental":[90],"measurements":[91],"implementations":[96],"in":[97,133],"silicon":[98],"FPGA,":[100],"validating":[101],"proposed":[103],"features.":[105],"was":[109,131],"implemented":[110],"into":[111],"full":[113],"32-bit":[117],"RISC-V":[118],"based":[119],"core,":[120],"AHB":[122],"bus,":[123,126],"APB":[125],"peripherals.":[128],"fabricated":[132],"general-purpose":[135],"0.18\u03bcm":[136],"CMOS":[137],"technology,":[138],"where":[139],"occupies":[143],"5.8%":[144],"of":[145],"total":[147],"area.":[149]},"counts_by_year":[{"year":2023,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}