{"id":"https://openalex.org/W2811116664","doi":"https://doi.org/10.1109/lascas.2018.8399923","title":"FPGA implementation of high-performance asynchronous pipelines with robust control","display_name":"FPGA implementation of high-performance asynchronous pipelines with robust control","publication_year":2018,"publication_date":"2018-02-01","ids":{"openalex":"https://openalex.org/W2811116664","doi":"https://doi.org/10.1109/lascas.2018.8399923","mag":"2811116664"},"language":"en","primary_location":{"id":"doi:10.1109/lascas.2018.8399923","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lascas.2018.8399923","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5009078527","display_name":"Duarte L. Oliveira","orcid":null},"institutions":[{"id":"https://openalex.org/I4210123805","display_name":"Instituto de Aeron\u00e1utica e Espa\u00e7o","ror":"https://ror.org/025n1fp68","country_code":"BR","type":"other","lineage":["https://openalex.org/I4210123805"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"Duarte L. Oliveira","raw_affiliation_strings":["Electronic Engineer Division, Technological Institute of Aeronautics, Brazil"],"affiliations":[{"raw_affiliation_string":"Electronic Engineer Division, Technological Institute of Aeronautics, Brazil","institution_ids":["https://openalex.org/I4210123805"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027799000","display_name":"Kledermon Garcia","orcid":null},"institutions":[{"id":"https://openalex.org/I4210123805","display_name":"Instituto de Aeron\u00e1utica e Espa\u00e7o","ror":"https://ror.org/025n1fp68","country_code":"BR","type":"other","lineage":["https://openalex.org/I4210123805"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Kledermon Garcia","raw_affiliation_strings":["Division of Aeronautical Systems of the Institute of Aeronautics and Space, Brazil"],"affiliations":[{"raw_affiliation_string":"Division of Aeronautical Systems of the Institute of Aeronautics and Space, Brazil","institution_ids":["https://openalex.org/I4210123805"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074938609","display_name":"Lucas Santana","orcid":null},"institutions":[{"id":"https://openalex.org/I4210123805","display_name":"Instituto de Aeron\u00e1utica e Espa\u00e7o","ror":"https://ror.org/025n1fp68","country_code":"BR","type":"other","lineage":["https://openalex.org/I4210123805"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Lucas Santana","raw_affiliation_strings":["Electronic Engineer Division, Technological Institute of Aeronautics, Brazil"],"affiliations":[{"raw_affiliation_string":"Electronic Engineer Division, Technological Institute of Aeronautics, Brazil","institution_ids":["https://openalex.org/I4210123805"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112249506","display_name":"Lester A. Faria","orcid":null},"institutions":[{"id":"https://openalex.org/I4210123805","display_name":"Instituto de Aeron\u00e1utica e Espa\u00e7o","ror":"https://ror.org/025n1fp68","country_code":"BR","type":"other","lineage":["https://openalex.org/I4210123805"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Lester A. Faria","raw_affiliation_strings":["Electronic Engineer Division, Technological Institute of Aeronautics, Brazil"],"affiliations":[{"raw_affiliation_string":"Electronic Engineer Division, Technological Institute of Aeronautics, Brazil","institution_ids":["https://openalex.org/I4210123805"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5009078527"],"corresponding_institution_ids":["https://openalex.org/I4210123805"],"apc_list":null,"apc_paid":null,"fwci":0.1288,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.47019586,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.887124240398407},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8180207014083862},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.7721495032310486},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7654464244842529},{"id":"https://openalex.org/keywords/pipeline-transport","display_name":"Pipeline transport","score":0.7156953811645508},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5744812488555908},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5382013320922852},{"id":"https://openalex.org/keywords/asynchronous-system","display_name":"Asynchronous system","score":0.5132219791412354},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14958402514457703},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09511831402778625},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.08611747622489929}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.887124240398407},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8180207014083862},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.7721495032310486},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7654464244842529},{"id":"https://openalex.org/C175309249","wikidata":"https://www.wikidata.org/wiki/Q725864","display_name":"Pipeline transport","level":2,"score":0.7156953811645508},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5744812488555908},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5382013320922852},{"id":"https://openalex.org/C7923308","wikidata":"https://www.wikidata.org/wiki/Q4812211","display_name":"Asynchronous system","level":5,"score":0.5132219791412354},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14958402514457703},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09511831402778625},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08611747622489929},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C87717796","wikidata":"https://www.wikidata.org/wiki/Q146326","display_name":"Environmental engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/lascas.2018.8399923","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lascas.2018.8399923","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1554812212","https://openalex.org/W1577323490","https://openalex.org/W1975331880","https://openalex.org/W1998380797","https://openalex.org/W2040093980","https://openalex.org/W2050447126","https://openalex.org/W2092892712","https://openalex.org/W2095466411","https://openalex.org/W2111139814","https://openalex.org/W2111489015","https://openalex.org/W2120733705","https://openalex.org/W2127320223","https://openalex.org/W2132283882","https://openalex.org/W2137563608","https://openalex.org/W2143092926","https://openalex.org/W2144801428","https://openalex.org/W2160823654","https://openalex.org/W2178247634","https://openalex.org/W2554925461","https://openalex.org/W2573885435","https://openalex.org/W4231905827","https://openalex.org/W4250179167","https://openalex.org/W6683394555"],"related_works":["https://openalex.org/W4380433113","https://openalex.org/W4386072068","https://openalex.org/W252339960","https://openalex.org/W2390529043","https://openalex.org/W2985738161","https://openalex.org/W2378320433","https://openalex.org/W2358343511","https://openalex.org/W2071821326","https://openalex.org/W4312516786","https://openalex.org/W2051877971"],"abstract_inverted_index":{"Asynchronous":[0],"paradigm":[1],"is":[2,18,26,55],"an":[3,88],"option":[4],"for":[5,20,38,105],"digital":[6,40],"designs":[7],"and":[8,24,60,78],"there":[9],"are":[10,103],"several":[11],"design":[12],"styles.":[13],"The":[14,53],"asynchronous":[15,39,100],"pipeline":[16,45],"style":[17],"interesting":[19],"achieving":[21],"high":[22],"performance":[23],"it":[25],"a":[27,35],"simpler":[28],"design.":[29],"In":[30],"this":[31],"paper,":[32],"we":[33],"propose":[34],"robust":[36],"control":[37,54],"systems,":[41],"in":[42,74,79,93],"the":[43,62,65,75,84,98],"bundled-data":[44],"style,":[46],"considering":[47],"commercial":[48],"FPGAs":[49],"as":[50],"target":[51],"devices.":[52],"free":[56],"of":[57,64,83,91],"essential":[58],"hazard":[59],"without":[61],"assumption":[63],"fundamental":[66],"mode.":[67],"Five":[68],"signal":[69],"processing":[70],"benchmarks":[71],"were":[72],"implemented":[73],"proposed":[76],"architecture":[77],"two":[80,99],"other":[81],"architectures":[82],"literature.":[85],"It":[86],"achieved":[87],"average":[89],"increase":[90],"22.6%":[92],"throughput":[94],"when":[95],"compared":[96],"to":[97],"pipelines":[101],"that":[102],"suitable":[104],"FPGAs.":[106]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}