{"id":"https://openalex.org/W2810764774","doi":"https://doi.org/10.1109/lascas.2018.8399911","title":"Continuous time full-feedforward MASH 2-2 architecture for sigma-delta modulators","display_name":"Continuous time full-feedforward MASH 2-2 architecture for sigma-delta modulators","publication_year":2018,"publication_date":"2018-02-01","ids":{"openalex":"https://openalex.org/W2810764774","doi":"https://doi.org/10.1109/lascas.2018.8399911","mag":"2810764774"},"language":"en","primary_location":{"id":"doi:10.1109/lascas.2018.8399911","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lascas.2018.8399911","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE 9th Latin American Symposium on Circuits &amp; Systems (LASCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5045562272","display_name":"Walter Lancioni","orcid":null},"institutions":[{"id":"https://openalex.org/I130054616","display_name":"Universidad Cat\u00f3lica de C\u00f3rdoba","ror":"https://ror.org/04hehwn14","country_code":"AR","type":"education","lineage":["https://openalex.org/I130054616"]}],"countries":["AR"],"is_corresponding":false,"raw_author_name":"Walter Jose Lancioni","raw_affiliation_strings":["Microelectronics Laboratory, Universidad Cat\u00f3lica de C\u00f3rdoba (UCC), C\u00f3rdoba, Argentina"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microelectronics Laboratory, Universidad Cat\u00f3lica de C\u00f3rdoba (UCC), C\u00f3rdoba, Argentina","institution_ids":["https://openalex.org/I130054616"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007049793","display_name":"Fortunato Carlos Dualibe","orcid":"https://orcid.org/0000-0002-2889-315X"},"institutions":[{"id":"https://openalex.org/I130054616","display_name":"Universidad Cat\u00f3lica de C\u00f3rdoba","ror":"https://ror.org/04hehwn14","country_code":"AR","type":"education","lineage":["https://openalex.org/I130054616"]}],"countries":["AR"],"is_corresponding":false,"raw_author_name":"Fortunato Carlos Dualibe","raw_affiliation_strings":["Microelectronics Laboratory, Universidad Cat\u00f3lica de C\u00f3rdoba (UCC), C\u00f3rdoba, Argentina"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microelectronics Laboratory, Universidad Cat\u00f3lica de C\u00f3rdoba (UCC), C\u00f3rdoba, Argentina","institution_ids":["https://openalex.org/I130054616"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014235625","display_name":"Pablo Petrashin","orcid":"https://orcid.org/0000-0003-2607-6196"},"institutions":[{"id":"https://openalex.org/I130054616","display_name":"Universidad Cat\u00f3lica de C\u00f3rdoba","ror":"https://ror.org/04hehwn14","country_code":"AR","type":"education","lineage":["https://openalex.org/I130054616"]}],"countries":["AR"],"is_corresponding":false,"raw_author_name":"Pablo Petrashin","raw_affiliation_strings":["Microelectronics Laboratory, Universidad Cat\u00f3lica de C\u00f3rdoba (UCC), C\u00f3rdoba, Argentina"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microelectronics Laboratory, Universidad Cat\u00f3lica de C\u00f3rdoba (UCC), C\u00f3rdoba, Argentina","institution_ids":["https://openalex.org/I130054616"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022348000","display_name":"Luis Toledo","orcid":"https://orcid.org/0009-0001-4683-9835"},"institutions":[{"id":"https://openalex.org/I130054616","display_name":"Universidad Cat\u00f3lica de C\u00f3rdoba","ror":"https://ror.org/04hehwn14","country_code":"AR","type":"education","lineage":["https://openalex.org/I130054616"]}],"countries":["AR"],"is_corresponding":false,"raw_author_name":"Luis Toledo","raw_affiliation_strings":["Microelectronics Laboratory, Universidad Cat\u00f3lica de C\u00f3rdoba (UCC), C\u00f3rdoba, Argentina"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microelectronics Laboratory, Universidad Cat\u00f3lica de C\u00f3rdoba (UCC), C\u00f3rdoba, Argentina","institution_ids":["https://openalex.org/I130054616"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072405063","display_name":"Carlos Andr\u00e9s Garc\u00eda\u2010V\u00e1zquez","orcid":"https://orcid.org/0000-0002-0544-6293"},"institutions":[{"id":"https://openalex.org/I130929987","display_name":"University of Mons","ror":"https://ror.org/02qnnz951","country_code":"BE","type":"education","lineage":["https://openalex.org/I130929987"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Carlos Vazquez","raw_affiliation_strings":["Electronics and Microelectronics Department (SEMi), Faculte Polytechnique (FPMS)-Universit\u00e9 de Mons (UMons), Mons, Belgium"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronics and Microelectronics Department (SEMi), Faculte Polytechnique (FPMS)-Universit\u00e9 de Mons (UMons), Mons, Belgium","institution_ids":["https://openalex.org/I130929987"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.0366,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.71008646,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/delta-sigma-modulation","display_name":"Delta-sigma modulation","score":0.8900859355926514},{"id":"https://openalex.org/keywords/integrator","display_name":"Integrator","score":0.861540675163269},{"id":"https://openalex.org/keywords/feed-forward","display_name":"Feed forward","score":0.8523199558258057},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5674120783805847},{"id":"https://openalex.org/keywords/control-theory","display_name":"Control theory (sociology)","score":0.5194072723388672},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5183271169662476},{"id":"https://openalex.org/keywords/noise-shaping","display_name":"Noise shaping","score":0.5132746696472168},{"id":"https://openalex.org/keywords/matlab","display_name":"MATLAB","score":0.49382123351097107},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.24908339977264404},{"id":"https://openalex.org/keywords/control-engineering","display_name":"Control engineering","score":0.24009469151496887},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.13150691986083984},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.0935228168964386},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08802983164787292},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.08009222149848938}],"concepts":[{"id":"https://openalex.org/C68754193","wikidata":"https://www.wikidata.org/wiki/Q1184820","display_name":"Delta-sigma modulation","level":3,"score":0.8900859355926514},{"id":"https://openalex.org/C79518650","wikidata":"https://www.wikidata.org/wiki/Q2081431","display_name":"Integrator","level":3,"score":0.861540675163269},{"id":"https://openalex.org/C38858127","wikidata":"https://www.wikidata.org/wiki/Q5441228","display_name":"Feed forward","level":2,"score":0.8523199558258057},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5674120783805847},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.5194072723388672},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5183271169662476},{"id":"https://openalex.org/C9083635","wikidata":"https://www.wikidata.org/wiki/Q2133535","display_name":"Noise shaping","level":2,"score":0.5132746696472168},{"id":"https://openalex.org/C2780365114","wikidata":"https://www.wikidata.org/wiki/Q169478","display_name":"MATLAB","level":2,"score":0.49382123351097107},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24908339977264404},{"id":"https://openalex.org/C133731056","wikidata":"https://www.wikidata.org/wiki/Q4917288","display_name":"Control engineering","level":1,"score":0.24009469151496887},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.13150691986083984},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.0935228168964386},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08802983164787292},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.08009222149848938},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/lascas.2018.8399911","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lascas.2018.8399911","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE 9th Latin American Symposium on Circuits &amp; Systems (LASCAS)","raw_type":"proceedings-article"},{"id":"pmh:oai:orbi.umons.ac.be:20.500.12907/42129","is_oa":false,"landing_page_url":"https://orbi.umons.ac.be/handle/20.500.12907/42129","pdf_url":null,"source":{"id":"https://openalex.org/S7407055454","display_name":"ORBi UMONS","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Latin Americn Syposium on Circuits and Systems, Puerto Vallarta, Mexico [MX], 2018","raw_type":"http://purl.org/coar/resource_type/c_5794"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.6200000047683716,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W55810901","https://openalex.org/W245245344","https://openalex.org/W1501863144","https://openalex.org/W1545507897","https://openalex.org/W1600634902","https://openalex.org/W2022850575","https://openalex.org/W2103121821","https://openalex.org/W2162130828","https://openalex.org/W2166948256","https://openalex.org/W2243588167","https://openalex.org/W6602327018"],"related_works":["https://openalex.org/W2157118673","https://openalex.org/W2016777110","https://openalex.org/W1624221390","https://openalex.org/W2097407725","https://openalex.org/W2548491887","https://openalex.org/W2955641057","https://openalex.org/W2031274516","https://openalex.org/W1976391040","https://openalex.org/W2913428688","https://openalex.org/W3097708393"],"abstract_inverted_index":{"In":[0,42],"this":[1,43],"work,":[2],"the":[3,49,62,67,77,83,86,108],"design":[4,28],"of":[5,9,51,85],"a":[6],"new":[7],"architecture":[8],"Continuous":[10],"Time":[11],"(CT)":[12],"MASH":[13,45],"2-2":[14],"(multi-stage":[15],"noise":[16],"shaping":[17],"modulators)":[18],"full":[19],"feedforward":[20,58],"Sigma":[21],"Delta":[22],"(\u03a3\u0394)":[23],"modulator":[24],"is":[25,29],"presented.":[26],"This":[27,72],"carried":[30],"out":[31],"by":[32,102],"using":[33,104],"Discrete-Time":[34],"(DT)":[35],"first":[36],"and":[37,70,79,94,107],"Impulse-Invariant":[38],"transformation":[39],"techniques":[40],"later.":[41],"proposal,":[44],"structures,":[46],"that":[47],"allows":[48],"implementation":[50],"stable":[52],"high-order":[53],"modulators,":[54],"are":[55,100],"combined":[56],"with":[57],"architectures":[59],"which":[60],"reduce":[61,76],"signal":[63],"ranges":[64],"required":[65],"at":[66,82],"integrators":[68],"inputs":[69],"outputs.":[71],"combination":[73],"leads":[74],"to":[75],"swing":[78],"slewing":[80],"requirements":[81],"output":[84],"integrators,":[87],"making":[88],"it":[89],"ideal":[90],"for":[91],"low":[92,95],"voltage":[93],"power":[96],"applications.":[97],"Theoretical":[98],"results":[99],"verified":[101],"simulations":[103],"Matlab,":[105],"Simulink":[106],"specific":[109],"CAD":[110],"SIMSIDES":[111],"[1].":[112]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
