{"id":"https://openalex.org/W4417170179","doi":"https://doi.org/10.1109/jssc.2025.3639747","title":"A 3-nm FinFET 563-kbit 35.5-Mbit/mm <sup>2</sup> Dual-Rail SRAM With 3.89-pJ/Access High Energy Efficient and 27.5-\u03bcW/Mbit One-Cycle Latency Low-Leakage Mode","display_name":"A 3-nm FinFET 563-kbit 35.5-Mbit/mm <sup>2</sup> Dual-Rail SRAM With 3.89-pJ/Access High Energy Efficient and 27.5-\u03bcW/Mbit One-Cycle Latency Low-Leakage Mode","publication_year":2025,"publication_date":"2025-12-09","ids":{"openalex":"https://openalex.org/W4417170179","doi":"https://doi.org/10.1109/jssc.2025.3639747"},"language":null,"primary_location":{"id":"doi:10.1109/jssc.2025.3639747","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2025.3639747","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101472624","display_name":"Y. Aoyagi","orcid":"https://orcid.org/0009-0000-6406-1601"},"institutions":[{"id":"https://openalex.org/I4210091154","display_name":"Technology Management Company (United States)","ror":"https://ror.org/00gvkt544","country_code":"US","type":"company","lineage":["https://openalex.org/I4210091154"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yumito Aoyagi","raw_affiliation_strings":["Japan Memory Design Program, Memory Solution Division, TSMC Design Technology Japan, Inc., Yokohama, Kanagawa, Japan"],"raw_orcid":"https://orcid.org/0009-0000-6406-1601","affiliations":[{"raw_affiliation_string":"Japan Memory Design Program, Memory Solution Division, TSMC Design Technology Japan, Inc., Yokohama, Kanagawa, Japan","institution_ids":["https://openalex.org/I4210091154"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047952713","display_name":"Koji Nii","orcid":"https://orcid.org/0000-0002-9986-5308"},"institutions":[{"id":"https://openalex.org/I4210091154","display_name":"Technology Management Company (United States)","ror":"https://ror.org/00gvkt544","country_code":"US","type":"company","lineage":["https://openalex.org/I4210091154"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Koji Nii","raw_affiliation_strings":["Japan Memory Design Program, Memory Solution Division, TSMC Design Technology Japan, Inc., Yokohama, Kanagawa, Japan"],"raw_orcid":"https://orcid.org/0000-0002-9986-5308","affiliations":[{"raw_affiliation_string":"Japan Memory Design Program, Memory Solution Division, TSMC Design Technology Japan, Inc., Yokohama, Kanagawa, Japan","institution_ids":["https://openalex.org/I4210091154"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088276903","display_name":"Makoto Yabuuchi","orcid":"https://orcid.org/0000-0003-1515-4726"},"institutions":[{"id":"https://openalex.org/I4210091154","display_name":"Technology Management Company (United States)","ror":"https://ror.org/00gvkt544","country_code":"US","type":"company","lineage":["https://openalex.org/I4210091154"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Makoto Yabuuchi","raw_affiliation_strings":["Japan Memory Design Program, Memory Solution Division, TSMC Design Technology Japan, Inc., Yokohama, Kanagawa, Japan"],"raw_orcid":"https://orcid.org/0000-0003-1515-4726","affiliations":[{"raw_affiliation_string":"Japan Memory Design Program, Memory Solution Division, TSMC Design Technology Japan, Inc., Yokohama, Kanagawa, Japan","institution_ids":["https://openalex.org/I4210091154"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103032021","display_name":"Tomotaka Tanaka","orcid":"https://orcid.org/0009-0009-0000-227X"},"institutions":[{"id":"https://openalex.org/I4210091154","display_name":"Technology Management Company (United States)","ror":"https://ror.org/00gvkt544","country_code":"US","type":"company","lineage":["https://openalex.org/I4210091154"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tomotaka Tanaka","raw_affiliation_strings":["Japan Memory Design Program, Memory Solution Division, TSMC Design Technology Japan, Inc., Yokohama, Kanagawa, Japan"],"raw_orcid":"https://orcid.org/0009-0009-0000-227X","affiliations":[{"raw_affiliation_string":"Japan Memory Design Program, Memory Solution Division, TSMC Design Technology Japan, Inc., Yokohama, Kanagawa, Japan","institution_ids":["https://openalex.org/I4210091154"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112525929","display_name":"Kazuto Mizutani","orcid":null},"institutions":[{"id":"https://openalex.org/I4210091154","display_name":"Technology Management Company (United States)","ror":"https://ror.org/00gvkt544","country_code":"US","type":"company","lineage":["https://openalex.org/I4210091154"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kazuto Mizutani","raw_affiliation_strings":["Japan Memory Design Program, Memory Solution Division, TSMC Design Technology Japan, Inc., Yokohama, Kanagawa, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Japan Memory Design Program, Memory Solution Division, TSMC Design Technology Japan, Inc., Yokohama, Kanagawa, Japan","institution_ids":["https://openalex.org/I4210091154"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083428438","display_name":"Masaya Hamada","orcid":"https://orcid.org/0000-0002-5830-5283"},"institutions":[{"id":"https://openalex.org/I4210091154","display_name":"Technology Management Company (United States)","ror":"https://ror.org/00gvkt544","country_code":"US","type":"company","lineage":["https://openalex.org/I4210091154"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Masaya Hamada","raw_affiliation_strings":["Japan Memory Design Program, Memory Solution Division, TSMC Design Technology Japan, Inc., Yokohama, Kanagawa, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Japan Memory Design Program, Memory Solution Division, TSMC Design Technology Japan, Inc., Yokohama, Kanagawa, Japan","institution_ids":["https://openalex.org/I4210091154"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102538016","display_name":"Yuichiro Ishii","orcid":null},"institutions":[{"id":"https://openalex.org/I4210091154","display_name":"Technology Management Company (United States)","ror":"https://ror.org/00gvkt544","country_code":"US","type":"company","lineage":["https://openalex.org/I4210091154"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yuichiro Ishii","raw_affiliation_strings":["Japan Memory Design Program, Memory Solution Division, TSMC Design Technology Japan, Inc., Yokohama, Kanagawa, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Japan Memory Design Program, Memory Solution Division, TSMC Design Technology Japan, Inc., Yokohama, Kanagawa, Japan","institution_ids":["https://openalex.org/I4210091154"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Yen Chi Chou","orcid":null},"institutions":[{"id":"https://openalex.org/I4210120917","display_name":"Taiwan Semiconductor Manufacturing Company (Taiwan)","ror":"https://ror.org/02wx79d08","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210120917"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yen Chi Chou","raw_affiliation_strings":["Taiwan Semiconductor Manufacturing Company Ltd.,, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Taiwan Semiconductor Manufacturing Company Ltd.,, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210120917"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021856421","display_name":"Jun Cheng Liu","orcid":"https://orcid.org/0000-0003-0407-5619"},"institutions":[{"id":"https://openalex.org/I4210120917","display_name":"Taiwan Semiconductor Manufacturing Company (Taiwan)","ror":"https://ror.org/02wx79d08","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210120917"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jun Cheng Liu","raw_affiliation_strings":["Taiwan Semiconductor Manufacturing Company Ltd.,, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Taiwan Semiconductor Manufacturing Company Ltd.,, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210120917"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102016814","display_name":"Chien\u2010Yu Huang","orcid":"https://orcid.org/0000-0001-6341-5471"},"institutions":[{"id":"https://openalex.org/I4210120917","display_name":"Taiwan Semiconductor Manufacturing Company (Taiwan)","ror":"https://ror.org/02wx79d08","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210120917"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chien-Yu Huang","raw_affiliation_strings":["Taiwan Semiconductor Manufacturing Company Ltd.,, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Taiwan Semiconductor Manufacturing Company Ltd.,, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210120917"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020047064","display_name":"Kang-Hui Peng","orcid":null},"institutions":[{"id":"https://openalex.org/I4210120917","display_name":"Taiwan Semiconductor Manufacturing Company (Taiwan)","ror":"https://ror.org/02wx79d08","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210120917"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Kang-Hui Peng","raw_affiliation_strings":["Taiwan Semiconductor Manufacturing Company Ltd.,, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Taiwan Semiconductor Manufacturing Company Ltd.,, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210120917"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102914090","display_name":"Yu-Hao Hsu","orcid":"https://orcid.org/0000-0002-3165-1960"},"institutions":[{"id":"https://openalex.org/I4210120917","display_name":"Taiwan Semiconductor Manufacturing Company (Taiwan)","ror":"https://ror.org/02wx79d08","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210120917"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yu-Hao Hsu","raw_affiliation_strings":["Taiwan Semiconductor Manufacturing Company Ltd.,, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Taiwan Semiconductor Manufacturing Company Ltd.,, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210120917"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108900246","display_name":"Isabel Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I4210120917","display_name":"Taiwan Semiconductor Manufacturing Company (Taiwan)","ror":"https://ror.org/02wx79d08","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210120917"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Isabel Wang","raw_affiliation_strings":["Taiwan Semiconductor Manufacturing Company Ltd.,, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Taiwan Semiconductor Manufacturing Company Ltd.,, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210120917"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102615711","display_name":"Hong-Chen Cheng","orcid":null},"institutions":[{"id":"https://openalex.org/I4210120917","display_name":"Taiwan Semiconductor Manufacturing Company (Taiwan)","ror":"https://ror.org/02wx79d08","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210120917"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Hong-Chen Cheng","raw_affiliation_strings":["Taiwan Semiconductor Manufacturing Company Ltd.,, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Taiwan Semiconductor Manufacturing Company Ltd.,, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210120917"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102320565","display_name":"Hung-Jen Liao","orcid":null},"institutions":[{"id":"https://openalex.org/I4210120917","display_name":"Taiwan Semiconductor Manufacturing Company (Taiwan)","ror":"https://ror.org/02wx79d08","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210120917"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Hung-Jen Liao","raw_affiliation_strings":["Taiwan Semiconductor Manufacturing Company Ltd.,, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Taiwan Semiconductor Manufacturing Company Ltd.,, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210120917"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5114087240","display_name":"Tsung-Yung Jonathan Chang","orcid":"https://orcid.org/0009-0007-6505-5474"},"institutions":[{"id":"https://openalex.org/I4210120917","display_name":"Taiwan Semiconductor Manufacturing Company (Taiwan)","ror":"https://ror.org/02wx79d08","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210120917"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Tsung-Yung Jonathan Chang","raw_affiliation_strings":["Taiwan Semiconductor Manufacturing Company Ltd.,, Hsinchu, Taiwan"],"raw_orcid":"https://orcid.org/0009-0007-6505-5474","affiliations":[{"raw_affiliation_string":"Taiwan Semiconductor Manufacturing Company Ltd.,, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210120917"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":16,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.34028632,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"61","issue":"4","first_page":"1466","last_page":"1476"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9664000272750854,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9664000272750854,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.011500000022351742,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.008799999952316284,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/standby-power","display_name":"Standby power","score":0.8259999752044678},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7120000123977661},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5964000225067139},{"id":"https://openalex.org/keywords/efficient-energy-use","display_name":"Efficient energy use","score":0.5631999969482422},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.5353000164031982},{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.4569999873638153},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.43529999256134033},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.43160000443458557},{"id":"https://openalex.org/keywords/energy","display_name":"Energy (signal processing)","score":0.37610000371932983}],"concepts":[{"id":"https://openalex.org/C7140552","wikidata":"https://www.wikidata.org/wiki/Q1366402","display_name":"Standby power","level":3,"score":0.8259999752044678},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7120000123977661},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5964000225067139},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.5631999969482422},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.54339998960495},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.5353000164031982},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4733000099658966},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.4569999873638153},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.44130000472068787},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.43529999256134033},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.43160000443458557},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4237000048160553},{"id":"https://openalex.org/C186370098","wikidata":"https://www.wikidata.org/wiki/Q442787","display_name":"Energy (signal processing)","level":2,"score":0.37610000371932983},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3382999897003174},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.33379998803138733},{"id":"https://openalex.org/C46637626","wikidata":"https://www.wikidata.org/wiki/Q6693015","display_name":"Low latency (capital markets)","level":2,"score":0.3328000009059906},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.32409998774528503},{"id":"https://openalex.org/C2987719587","wikidata":"https://www.wikidata.org/wiki/Q1811428","display_name":"Leakage power","level":4,"score":0.3240000009536743},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.3165999948978424},{"id":"https://openalex.org/C2985973956","wikidata":"https://www.wikidata.org/wiki/Q1617745","display_name":"High energy","level":2,"score":0.30149999260902405},{"id":"https://openalex.org/C118993495","wikidata":"https://www.wikidata.org/wiki/Q5042828","display_name":"Electrical efficiency","level":3,"score":0.2815999984741211},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.26919999718666077},{"id":"https://openalex.org/C57149124","wikidata":"https://www.wikidata.org/wiki/Q587346","display_name":"Sleep mode","level":4,"score":0.25949999690055847},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2565999925136566},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2565000057220459},{"id":"https://openalex.org/C2780165032","wikidata":"https://www.wikidata.org/wiki/Q16869822","display_name":"Energy consumption","level":2,"score":0.25600001215934753},{"id":"https://openalex.org/C2776047111","wikidata":"https://www.wikidata.org/wiki/Q632037","display_name":"Dynamic voltage scaling","level":3,"score":0.2522999942302704}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2025.3639747","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2025.3639747","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"This":[0],"article":[1],"presents":[2],"a":[3,41,60,79,99,126,181],"high-density":[4],"(HD)":[5],"6T":[6],"SRAM":[7],"macro":[8,145],"designed":[9],"in":[10,35,134,188],"3-nm":[11],"FinFET":[12],"technology":[13],"with":[14,116],"an":[15,130],"extended":[16],"dual-rail":[17],"(XDR)":[18],"architecture,":[19],"addressing":[20],"active":[21,136],"energy":[22,52,171],"and":[23,40,88,119,168,185],"leakage":[24,159],"for":[25,183],"mobile":[26],"applications.":[27],"Two":[28],"key":[29],"innovations":[30],"are":[31],"introduced:":[32],"the":[33],"delayed-wordline":[34],"write":[36,76],"operation":[37],"(DEWL)":[38],"technique":[39],"one-cycle":[42],"latency":[43,118],"low-leakage":[44],"access":[45],"mode":[46],"(1-CLM).":[47],"The":[48,92,144],"XDR":[49],"architecture":[50],"enhances":[51],"efficiency":[53],"by":[54,83,102],"operating":[55],"most":[56],"peripheral":[57],"circuitry":[58],"at":[59,160,172],"lower":[61],"<inline-formula":[62,161,173],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[63,148,152,162,174],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">":[64,153,163,175],"<tex-math":[65,154,164,176],"notation=\"LaTeX\">$V_{\\text":[66],"{chip}}$</tex-math>":[67],"</inline-formula>":[68],"without":[69],"dedicated":[70],"level":[71],"shifters":[72],"(L/S).":[73],"DEWL":[74],"resolves":[75],"contention,":[77],"achieving":[78],"38%":[80],"write-power":[81],"reduction":[82,101,133],"reducing":[84],"dummy":[85],"read":[86],"power":[87],"minimizing":[89],"boost":[90],"capacitance.":[91],"1-CLM":[93],"significantly":[94],"improves":[95],"standby":[96,158],"leakage,":[97],"demonstrating":[98,180],"10%":[100],"turning":[103],"off":[104],"bitline":[105],"(BL)":[106],"pre-chargers":[107],"during":[108],"no-operation":[109],"(NOP)":[110],"cycles,":[111],"while":[112],"ensuring":[113],"rapid":[114],"wake-up":[115],"minimal":[117],"peak":[120],"current.":[121],"Fabricated":[122],"silicon":[123],"results":[124],"from":[125],"563-kbit":[127],"prototype":[128],"show":[129],"impressive":[131],"36%":[132],"average":[135],"energy,":[137],"3.89":[138],"pJ/access,":[139],"compared":[140],"to":[141],"conventional":[142],"designs.":[143],"achieves":[146],"35.5-Mbit/mm<sup":[147],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[149],"density,":[150],"27.5-<inline-formula":[151],"notation=\"LaTeX\">$\\mu":[155],"$</tex-math>":[156],"</inline-formula>W/Mbit":[157],"notation=\"LaTeX\">$25~^{\\circ":[165],"}$</tex-math>":[166,178],"</inline-formula>C,":[167,179],"6.94-pJ/access/Mbit":[169],"total":[170],"notation=\"LaTeX\">$85~^{\\circ":[177],"solution":[182],"energy-efficient":[184],"reliable":[186],"SRAMs":[187],"aggressively":[189],"scaled":[190],"technologies.":[191]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-12-09T00:00:00"}
