{"id":"https://openalex.org/W4415883333","doi":"https://doi.org/10.1109/jssc.2025.3623630","title":"SHINSAI: A 586 mm <sup>2</sup> Reusable Active TSV Interposer With Programmable Interconnect Fabric and 512 Mb Underdeck Memory","display_name":"SHINSAI: A 586 mm <sup>2</sup> Reusable Active TSV Interposer With Programmable Interconnect Fabric and 512 Mb Underdeck Memory","publication_year":2025,"publication_date":"2025-11-04","ids":{"openalex":"https://openalex.org/W4415883333","doi":"https://doi.org/10.1109/jssc.2025.3623630"},"language":null,"primary_location":{"id":"doi:10.1109/jssc.2025.3623630","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2025.3623630","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037971089","display_name":"Haozhe Zhu","orcid":"https://orcid.org/0000-0002-6412-3996"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Haozhe Zhu","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"],"raw_orcid":"https://orcid.org/0000-0002-6412-3996","affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079670597","display_name":"Bo Jiao","orcid":"https://orcid.org/0000-0002-8173-8060"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Bo Jiao","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089740254","display_name":"Youyi Zeng","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuman Zeng","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"],"raw_orcid":"https://orcid.org/0009-0001-5290-7670","affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101752493","display_name":"Yongjiang Li","orcid":"https://orcid.org/0000-0001-9247-573X"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yongjiang Li","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018860020","display_name":"Jie Liao","orcid":"https://orcid.org/0000-0002-6697-8998"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jie Liao","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Siyao Jia","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Siyao Jia","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Zexing Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zexing Chen","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061386400","display_name":"Liyu Lin","orcid":"https://orcid.org/0000-0001-8663-7448"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Liyu Lin","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113058728","display_name":"Xuanda Lin","orcid":"https://orcid.org/0009-0009-6355-2439"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xuanda Lin","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"],"raw_orcid":"https://orcid.org/0009-0009-6355-2439","affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109405513","display_name":"S. H. Huang","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Suchang Huang","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5116535142","display_name":"Mochen Tian","orcid":null},"institutions":[{"id":"https://openalex.org/I4210119559","display_name":"Taiwan Semiconductor Manufacturing Company (China)","ror":"https://ror.org/02s0wcj29","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210119559","https://openalex.org/I4210120917"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Mochen Tian","raw_affiliation_strings":["Kiwimoore Semiconductors Company Ltd., Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Kiwimoore Semiconductors Company Ltd., Shanghai, China","institution_ids":["https://openalex.org/I4210119559"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101960346","display_name":"Jundong Zhu","orcid":"https://orcid.org/0000-0002-0104-2507"},"institutions":[{"id":"https://openalex.org/I4210119559","display_name":"Taiwan Semiconductor Manufacturing Company (China)","ror":"https://ror.org/02s0wcj29","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210119559","https://openalex.org/I4210120917"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jundong Zhu","raw_affiliation_strings":["Kiwimoore Semiconductors Company Ltd., Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Kiwimoore Semiconductors Company Ltd., Shanghai, China","institution_ids":["https://openalex.org/I4210119559"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111248827","display_name":"D.S. Wen","orcid":null},"institutions":[{"id":"https://openalex.org/I4210119559","display_name":"Taiwan Semiconductor Manufacturing Company (China)","ror":"https://ror.org/02s0wcj29","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210119559","https://openalex.org/I4210120917"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Dexin Wen","raw_affiliation_strings":["Kiwimoore Semiconductors Company Ltd., Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Kiwimoore Semiconductors Company Ltd., Shanghai, China","institution_ids":["https://openalex.org/I4210119559"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100322651","display_name":"Yan Wang","orcid":"https://orcid.org/0000-0002-3073-2590"},"institutions":[{"id":"https://openalex.org/I4210119559","display_name":"Taiwan Semiconductor Manufacturing Company (China)","ror":"https://ror.org/02s0wcj29","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210119559","https://openalex.org/I4210120917"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yan Wang","raw_affiliation_strings":["Kiwimoore Semiconductors Company Ltd., Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Kiwimoore Semiconductors Company Ltd., Shanghai, China","institution_ids":["https://openalex.org/I4210119559"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100445347","display_name":"Yu Wang","orcid":"https://orcid.org/0000-0003-1777-2050"},"institutions":[{"id":"https://openalex.org/I4210119559","display_name":"Taiwan Semiconductor Manufacturing Company (China)","ror":"https://ror.org/02s0wcj29","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210119559","https://openalex.org/I4210120917"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yu Wang","raw_affiliation_strings":["Kiwimoore Semiconductors Company Ltd., Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Kiwimoore Semiconductors Company Ltd., Shanghai, China","institution_ids":["https://openalex.org/I4210119559"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044446232","display_name":"Jian Xu","orcid":"https://orcid.org/0000-0002-6595-8602"},"institutions":[{"id":"https://openalex.org/I4210119559","display_name":"Taiwan Semiconductor Manufacturing Company (China)","ror":"https://ror.org/02s0wcj29","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210119559","https://openalex.org/I4210120917"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jian Xu","raw_affiliation_strings":["Kiwimoore Semiconductors Company Ltd., Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Kiwimoore Semiconductors Company Ltd., Shanghai, China","institution_ids":["https://openalex.org/I4210119559"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038260988","display_name":"Feng Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I4210119559","display_name":"Taiwan Semiconductor Manufacturing Company (China)","ror":"https://ror.org/02s0wcj29","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210119559","https://openalex.org/I4210120917"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Feng Wang","raw_affiliation_strings":["Kiwimoore Semiconductors Company Ltd., Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Kiwimoore Semiconductors Company Ltd., Shanghai, China","institution_ids":["https://openalex.org/I4210119559"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062927280","display_name":"Jun Tao","orcid":"https://orcid.org/0000-0001-8742-687X"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jun Tao","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"],"raw_orcid":"https://orcid.org/0000-0001-8742-687X","affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051205321","display_name":"Chixiao Chen","orcid":"https://orcid.org/0000-0002-5980-4236"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chixiao Chen","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"],"raw_orcid":"https://orcid.org/0000-0002-5980-4236","affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100453158","display_name":"Qi Liu","orcid":"https://orcid.org/0000-0001-7062-831X"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Qi Liu","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"],"raw_orcid":"https://orcid.org/0000-0001-7062-831X","affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110532530","display_name":"Ming Liu","orcid":"https://orcid.org/0000-0002-3419-4400"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ming Liu","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.4626,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.6946324,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":97},"biblio":{"volume":"61","issue":"1","first_page":"90","last_page":"102"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9940999746322632,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9940999746322632,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.002099999925121665,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10460","display_name":"Electronic Packaging and Soldering Technologies","score":0.0012000000569969416,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interposer","display_name":"Interposer","score":0.8449000120162964},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6496000289916992},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.6092000007629395},{"id":"https://openalex.org/keywords/reuse","display_name":"Reuse","score":0.49950000643730164},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.4625000059604645},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.4607999920845032},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.3878999948501587}],"concepts":[{"id":"https://openalex.org/C158802814","wikidata":"https://www.wikidata.org/wiki/Q6056418","display_name":"Interposer","level":4,"score":0.8449000120162964},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6496000289916992},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.6092000007629395},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6064000129699707},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5879999995231628},{"id":"https://openalex.org/C206588197","wikidata":"https://www.wikidata.org/wiki/Q846574","display_name":"Reuse","level":2,"score":0.49950000643730164},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4749000072479248},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.4625000059604645},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.4607999920845032},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.3878999948501587},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.3862000107765198},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.3621000051498413},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.3334999978542328},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.32760000228881836},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3140999972820282},{"id":"https://openalex.org/C2779585090","wikidata":"https://www.wikidata.org/wiki/Q3457762","display_name":"Resilience (materials science)","level":2,"score":0.3138999938964844},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.3082999885082245},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.259799987077713},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.25920000672340393},{"id":"https://openalex.org/C32833848","wikidata":"https://www.wikidata.org/wiki/Q4115054","display_name":"Extensibility","level":2,"score":0.2524000108242035},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.2517000138759613}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2025.3623630","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2025.3623630","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G4906109994","display_name":null,"funder_award_id":"62488101","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G5218974994","display_name":null,"funder_award_id":"2024ZY2B0070","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W38262683","https://openalex.org/W2044902313","https://openalex.org/W2060510412","https://openalex.org/W2518432791","https://openalex.org/W2532719504","https://openalex.org/W2970916899","https://openalex.org/W2996407519","https://openalex.org/W3015587302","https://openalex.org/W3016212306","https://openalex.org/W3111684448","https://openalex.org/W3187148842","https://openalex.org/W3191415913","https://openalex.org/W4220943275","https://openalex.org/W4220972538","https://openalex.org/W4221013705","https://openalex.org/W4221089937","https://openalex.org/W4237926084","https://openalex.org/W4297097347","https://openalex.org/W4297097382","https://openalex.org/W4297097464","https://openalex.org/W4360605760","https://openalex.org/W4380874786","https://openalex.org/W4385525225","https://openalex.org/W4392746141","https://openalex.org/W4400314928","https://openalex.org/W4402475781","https://openalex.org/W4402475823","https://openalex.org/W4402475847","https://openalex.org/W4408183445"],"related_works":[],"abstract_inverted_index":{"This":[0],"article":[1],"presents":[2],"SHINSAI\u2014a":[3],"586":[4],"mm<sup":[5],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[6,96,102,141,149],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[7],"reusable":[8],"active":[9,23],"through-silicon":[10],"via":[11],"(TSV)":[12],"interposer":[13],"addressing":[14],"key":[15,73],"challenges":[16],"in":[17,132],"multi-chiplet":[18],"integration":[19],"(MCI)":[20],"architectures.":[21],"While":[22],"interposers":[24,48],"overcome":[25],"fundamental":[26],"limitations":[27,56],"of":[28,147],"passive":[29],"counterparts":[30],"by":[31],"integrating":[32,120],"functional":[33],"circuitry,":[34],"existing":[35],"solutions":[36],"face":[37],"three":[38,72],"critical":[39],"constraints:":[40],"1)":[41],"non-recurring":[42],"engineering":[43],"(NRE)":[44],"costs":[45],"from":[46],"application-specific":[47],"negating":[49],"chiplet":[50],"reuse":[51],"benefits;":[52],"2)":[53],"memory":[54],"capacity":[55],"restricting":[57],"compute":[58],"scalability;":[59],"and":[60,112],"3)":[61],"inflexible":[62],"interconnects":[63],"unable":[64],"to":[65,84],"support":[66],"diverse":[67],"communication":[68,86],"patterns.":[69],"SHINSAI":[70,129],"introduces":[71],"innovations:":[74],"a":[75,88,113,139],"heterogeneous":[76],"dual-layer":[77],"network-on-active-interposer":[78],"(NoAI)":[79],"combining":[80],"packet/circuit-switched":[81],"(CS)":[82],"paradigms":[83],"reduce":[85],"latency;":[87],"programmable":[89],"2.5-D":[90],"H-Link":[91],"fabric":[92],"enabling":[93],"protocol-agnostic":[94],"<inline-formula":[95,140,148],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">":[97,103,142,150],"<tex-math":[98,104,143,151],"notation=\"LaTeX\">$\\mu":[99,105,144],"$</tex-math>":[100,106,145,153],"</inline-formula>bump-to-<inline-formula":[101],"</inline-formula>bump":[107],"routing":[108],"across":[109],"arbitrary":[110],"topologies;":[111],"reconfigurable":[114],"3-D":[115],"vertical":[116],"link":[117],"(V-Link)":[118],"architecture":[119],"512":[121],"Mb":[122],"underdeck":[123],"SRAM":[124],"with":[125,135,138,160],"adaptive":[126],"bandwidth":[127],"allocation.":[128],"is":[130,163],"implemented":[131],"28-nm":[133],"CMOS":[134],"TSV-middle":[136],"technology,":[137],"</inline-formula>bump-pitch":[146],"notation=\"LaTeX\">$40~\\mu":[152],"</inline-formula>m.":[154],"A":[155],"SHINSAI-based":[156],"MCI":[157],"prototype":[158],"system":[159],"16":[161],"chiplets":[162],"also":[164],"assembled.":[165]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-11-04T00:00:00"}
