{"id":"https://openalex.org/W4415594238","doi":"https://doi.org/10.1109/jssc.2025.3615590","title":"0.021-\u03bcm <sup>2</sup> High-Density SRAM in Intel 18A RibbonFET Technology With PowerVia Backside Power Delivery","display_name":"0.021-\u03bcm <sup>2</sup> High-Density SRAM in Intel 18A RibbonFET Technology With PowerVia Backside Power Delivery","publication_year":2025,"publication_date":"2025-10-27","ids":{"openalex":"https://openalex.org/W4415594238","doi":"https://doi.org/10.1109/jssc.2025.3615590"},"language":null,"primary_location":{"id":"doi:10.1109/jssc.2025.3615590","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2025.3615590","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Xiaofei Wang","orcid":"https://orcid.org/0009-0005-1835-9665"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xiaofei Wang","raw_affiliation_strings":["Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":"https://orcid.org/0009-0005-1835-9665","affiliations":[{"raw_affiliation_string":"Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5116535539","display_name":"Gwang Hyeon Baek","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Gwang Hyeon Baek","raw_affiliation_strings":["Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5094136749","display_name":"Kunal Girish Bannore","orcid":"https://orcid.org/0009-0003-8954-3350"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kunal Girish Bannore","raw_affiliation_strings":["Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":"https://orcid.org/0009-0003-8954-3350","affiliations":[{"raw_affiliation_string":"Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Kaushal Pareshbhai Dave","orcid":"https://orcid.org/0009-0003-0861-8892"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kaushal Pareshbhai Dave","raw_affiliation_strings":["Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":"https://orcid.org/0009-0003-0861-8892","affiliations":[{"raw_affiliation_string":"Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032437900","display_name":"Arash Joushaghani","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Arash Joushaghani","raw_affiliation_strings":["Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Narae Kang","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Narae Kang","raw_affiliation_strings":["Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000094784","display_name":"Min-Woo Ko","orcid":"https://orcid.org/0000-0001-5901-6320"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Minwoo Ko","raw_affiliation_strings":["Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA","Advanced Design, Technology Development, Intel Corporation, Santa Clara, CA, USA"],"raw_orcid":"https://orcid.org/0000-0001-5901-6320","affiliations":[{"raw_affiliation_string":"Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Advanced Design, Technology Development, Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077144575","display_name":"Anandkumar Mahadevan Pillai","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Anandkumar Mahadevan Pillai","raw_affiliation_strings":["Advanced Design, Technology Development, Intel Corporation, Santa Clara, CA, USA","Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Design, Technology Development, Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062989399","display_name":"Hema C. P. Movva","orcid":"https://orcid.org/0000-0003-3001-3171"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hema Chandra Prakash Movva","raw_affiliation_strings":["Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":"https://orcid.org/0000-0003-3001-3171","affiliations":[{"raw_affiliation_string":"Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Gyusung Park","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Gyusung Park","raw_affiliation_strings":["Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Seenivasan Subramaniam","orcid":"https://orcid.org/0009-0004-5478-2228"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Seenivasan Subramaniam","raw_affiliation_strings":["Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":"https://orcid.org/0009-0004-5478-2228","affiliations":[{"raw_affiliation_string":"Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Vinay Vashishtha","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vinay Vashishtha","raw_affiliation_strings":["Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100773000","display_name":"Yang Teng","orcid":"https://orcid.org/0000-0002-6582-6167"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Teng Yang","raw_affiliation_strings":["Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007891380","display_name":"Zheng Guo","orcid":"https://orcid.org/0000-0001-8615-9749"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zheng Guo","raw_affiliation_strings":["Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":"https://orcid.org/0000-0001-8615-9749","affiliations":[{"raw_affiliation_string":"Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063387912","display_name":"Fatih Hamzaoglu","orcid":"https://orcid.org/0000-0003-3500-5007"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Fatih Hamzaoglu","raw_affiliation_strings":["Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":"https://orcid.org/0000-0003-3500-5007","affiliations":[{"raw_affiliation_string":"Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5053857493","display_name":"Eric Karl","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Eric A. Karl","raw_affiliation_strings":["Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.18737384,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"61","issue":"1","first_page":"259","last_page":"266"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9962000250816345,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.9135000109672546},{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.6453999876976013},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.5286999940872192},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.482699990272522},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.45840001106262207},{"id":"https://openalex.org/keywords/access-time","display_name":"Access time","score":0.44029998779296875},{"id":"https://openalex.org/keywords/memory-cell","display_name":"Memory cell","score":0.41929998993873596},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.36959999799728394}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.9135000109672546},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.6453999876976013},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.5286999940872192},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5156000256538391},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5019000172615051},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.482699990272522},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.45840001106262207},{"id":"https://openalex.org/C194080101","wikidata":"https://www.wikidata.org/wiki/Q46306","display_name":"Access time","level":2,"score":0.44029998779296875},{"id":"https://openalex.org/C2776638159","wikidata":"https://www.wikidata.org/wiki/Q18343761","display_name":"Memory cell","level":4,"score":0.41929998993873596},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4140999913215637},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3901999890804291},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.38029998540878296},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.36959999799728394},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3359000086784363},{"id":"https://openalex.org/C101722063","wikidata":"https://www.wikidata.org/wiki/Q218825","display_name":"Random access","level":2,"score":0.33000001311302185},{"id":"https://openalex.org/C46891859","wikidata":"https://www.wikidata.org/wiki/Q1061546","display_name":"Magnetoresistive random-access memory","level":3,"score":0.32190001010894775},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.29660001397132874},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.28839999437332153},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.27630001306533813},{"id":"https://openalex.org/C544956773","wikidata":"https://www.wikidata.org/wiki/Q670","display_name":"Silicon","level":2,"score":0.27469998598098755},{"id":"https://openalex.org/C92746544","wikidata":"https://www.wikidata.org/wiki/Q585184","display_name":"Pulse-width modulation","level":3,"score":0.26330000162124634},{"id":"https://openalex.org/C20556612","wikidata":"https://www.wikidata.org/wiki/Q4469374","display_name":"Volume (thermodynamics)","level":2,"score":0.2614000141620636},{"id":"https://openalex.org/C111106434","wikidata":"https://www.wikidata.org/wiki/Q1072430","display_name":"Die (integrated circuit)","level":2,"score":0.259799987077713},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.2574999928474426},{"id":"https://openalex.org/C43363307","wikidata":"https://www.wikidata.org/wiki/Q1651623","display_name":"Racetrack memory","level":5,"score":0.2529999911785126}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2025.3615590","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2025.3615590","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1996188635","https://openalex.org/W2014357578","https://openalex.org/W2048611611","https://openalex.org/W2752340955","https://openalex.org/W2789659455","https://openalex.org/W2899206356","https://openalex.org/W3015213341","https://openalex.org/W3134817854","https://openalex.org/W4244763807","https://openalex.org/W4313203552","https://openalex.org/W4385192500","https://openalex.org/W4385192573","https://openalex.org/W4392746305","https://openalex.org/W4401687401","https://openalex.org/W4401881618","https://openalex.org/W4408183030","https://openalex.org/W4412962799"],"related_works":[],"abstract_inverted_index":{"This":[0],"article":[1],"introduces":[2],"the":[3,68,78],"industry\u2019s":[4],"first":[5],"volume-production":[6],"silicon-validated":[7],"static":[8],"random":[9],"access":[10],"memory":[11],"(SRAM)":[12],"designs":[13,63],"fabricated":[14],"using":[15],"Intel\u2019s":[16],"18A":[17],"RibbonFET":[18],"technology,":[19],"incorporating":[20],"PowerVia":[21],"backside":[22],"power":[23],"delivery.":[24],"The":[25,97],"high-density":[26],"0.021-$\\mu":[27],"$m2SRAM":[28],"cell":[29,73],"achieves":[30],"an":[31],"array":[32],"density":[33],"of":[34],"up":[35,103],"to":[36,61,85,104],"38.1":[37],"Mb/mm2.":[38],"With":[39],"a":[40,101],"high":[41],"volume":[42],"34.3":[43],"Mb/mm2macro":[44],"implementation":[45],"in":[46,83],"silicon":[47],"demonstrating":[48],"improved":[49],"minimum":[50],"operation":[51],"voltage":[52],"($V_{\\mathrm":[53],"{MIN}}$)":[54],"with":[55],"negative":[56],"bitline":[57],"(NBL)":[58],"assist":[59,81,95],"compared":[60],"similar":[62],"on":[64],"FinFET":[65,87],"technology.":[66],"Additionally,":[67],"high-current":[69,72],"6T":[70],"SRAM":[71],"(HCC)":[74],"exhibits":[75],"improved$V_{\\mathrm":[76],"{MIN}}$without":[77],"need":[79],"for":[80],"techniques,":[82],"contrast":[84],"equivalent":[86],"implementations":[88],"that":[89],"require":[90],"both":[91],"read":[92],"and":[93],"write":[94],"mechanisms.":[96],"HCC":[98],"macro":[99],"demonstrates":[100],"frequency":[102],"5.6":[105],"GHz":[106],"when":[107],"operating":[108],"at":[109],"1.05":[110],"V.":[111]},"counts_by_year":[],"updated_date":"2026-07-29T09:40:50.615796","created_date":"2025-10-28T00:00:00"}